anonymous.
Junior Member level 3
I always use generics in my designs, for example I use WIDTH parameter with registers to specify how many bits it can hold, This has one problem though, If I need to use WIDTH=1 (a single Flip Flop) Design Compiler complains about signal assignment (Assigning std_logic from the top design to std_logic_vector from the register), Because this issue could happen at any stage of the design I decided to always replace all std_logics with std_logic_vector(0 downto 0) and that was it. Design Compiler never complains again about these.
Modelsim however does not accept this, this simple Mux example:
generates this error :
How to solve this issue in a manner that does not generate errors in both Design Compiler and Modelsim?
Modelsim however does not accept this, this simple Mux example:
Code:
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------
entity Mux_21 is
generic
(
WIDTH : integer := 8
);
port
(
FirstInput : in std_logic_vector(WIDTH-1 downto 0);
SecondInput : in std_logic_vector(WIDTH-1 downto 0);
Sel : in std_logic_vector(0 downto 0);
Output : out std_logic_vector(WIDTH-1 downto 0)
);
end entity; -- Mux_21
----------------------------------------
architecture Arch of Mux_21 is
begin
Output <= FirstInput when Sel = '0' else
SecondInput;
end architecture; -- Arch
generates this error :
Code:
No Feasible entries for infix operator "="
How to solve this issue in a manner that does not generate errors in both Design Compiler and Modelsim?