Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hey guys,
All my designs are in VHDL. I have place and routed the design using encounter. Now I want to extract the netlist and perform further analysis (functionality verification, power estimation with parasitics included). But the netlist is in verilog format and since other...
Hi,
I want to find frequency of operation for my_design at (i)Min area (ii)Max performance.
And my synthesis script is as follows:
analyze -f VHDL lib -work my_design.vhd
elborate my_design -library work
create_clock -name "clock1" -period N clk
set_max_area 0.0
insert_clock_gating
link...
Hey thanks for replying. I am trying to work on mainly finding the dynamic power consumption and leakage power. So I generally generate the ddc file and vcd file in cadence NCsim, dump it in Primetime PX. But while simulating the generated VHDL code, I saw every gate had zero delay from input to...
Hey,
I npticed a very unusual thing while simulating the gate level netlist to generate vcd file for power analysis. In the following example of decoder where I am taking the output at every clock edge, the VHDL source code is as following:
architecture behavior_decoder of decoder is
begin...
Hi,
I am using ncvhdl compiler 08.10-s019. I have been trying to simulate a package with a type that is declared as "protected" which is a part od vhdl 2002 feature. So in command line I tried simulating it as
ncvhdl -v200x -messages -work work const_pkg.vhd
But i am getting this error: type...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
