Simulating synthesised design of gate level netlist from Design compiler

[anjyothiswaroop]

Hey,
I npticed a very unusual thing while simulating the gate level netlist to generate vcd file for power analysis. In the following example of decoder where I am taking the output at every clock edge, the VHDL source code is as following:
architecture behavior_decoder of decoder is
begin

process ( inp,clk,rst )
begin

if (clk'event and clk = '1') then
if (rst = '1') then
oup <= "00000000";

else
case ( inp ) is
when "000" =>
oup <= "00000001";
when "001" =>
oup <= "00000010";
when "010" =>
oup <= "00000100";
when "011" =>
oup <= "00001000";
when "100" =>
oup <= "00010000";
when "101" =>
oup <= "00100000";
when "110" =>
oup <= "01000000";
when "111" =>
oup <= "10000000";
when others =>
oup <= "ZZZZZZZZ";
end case;
end if;
end if;
end process;

I synthesised gatelevel netlist for this RTl with tsmc 45nm library tcbn45gsbwp_120a/tcbn45gsbwpwc.db

Everything seemed to be fine till this point. When I checked the timing report I realised the time period must be 0.05 ns.
Point Incr Path
-----------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
input external delay 0.00 0.00 f
inp[0] (in) 0.00 0.00 f
U24/ZN (NR4D1BWP) 0.05 0.05 r
oup_reg[0]/D (DFQD1BWP) 0.00 0.05 r
data arrival time 0.05

clock clock1 (rise edge) 0.08 0.08
clock network delay (ideal) 0.00 0.08
oup_reg[0]/CP (DFQD1BWP) 0.00 0.08 r
library setup time -0.03 0.05
data required time 0.05
-----------------------------------------------------------
data required time 0.05
data arrival time -0.05
-----------------------------------------------------------
slack (MET) 0.00


When I tried simulating in cadence NCsim with a test-bench with clock period less than 0.05ns everything seems to be working fine. I compiled the tcbn library in the work library and then the netlist. Even when I tried with a very small clk period it seems to be fine. Where am I going wrong? Something seems to be not correct.

 

[girishbabu123]

Are u back annotating the sdf file for gate level simulation ?

 

[anjyothiswaroop]

Hey thanks for replying. I am trying to work on mainly finding the dynamic power consumption and leakage power. So I generally generate the ddc file and vcd file in cadence NCsim, dump it in Primetime PX. But while simulating the generated VHDL code, I saw every gate had zero delay from input to output, even when I gave extremely small clock period. When I was going through some forums I noticed that sdf file is mainly needed for timing anaysis and it needs to be definitely back annotated only for 0 delay simulation. Even other wise should it be annotated?
Many of the tutorials just give the procedure to do all these steps. Is there any site that explains in detail all these things?