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Hi Soway,
Sorry, I can't read Chinese. Could you just list me some potential solutions in detail? Thanks a lot!
I want to use RedHat AS or SUSE OS and run very big layout design.
Hi all!
We are looking for a low cost linux platform (PC is the best) EDA solution.
It have to run large layout design with pretty fast responds and can support linux OS very robust.
Could anybody recommand me the hardware list? More details hardware name or value will be very appreciated.
For...
Re: Is it possible to design a voltage regulator meet such s
Not yet. I still need help.
Could you share your idea with me?
I need very small area, so can't put a big capacitance on the output node...
But I also want to undershoot as small as possible when there is a big peak Iloading.
Thanks.
On chip design, 1.8V~2.5V input to 1.6V output
capacitance loading: 0~20pf
Peak current loading: 20mA (freq. 20Mhz)
undershoot deltV <100mV
Is it possible to get so small transient undershoot responds with less 10pf capacitance compensation on output node?
Thanks!
Thanks. How about the one stage folded cascode op for the EA and cascode miller compensation? Is it better than normal two stage EA for the good load transient reponse?
No, I mean what's the main factor to limit the load transient response performance? I find the drop voltage is big when there is a current loading peak.
Hi all,
Anybody can tell me how to reduce the undershoot when there is coming a peak current loading on a voltage regulator output? Is it only I can do just add output node capacitance as big as possible? Please help me. Thanks!
Regards,
Analog_Starter
Can anyone tell me how to design a high accuracy oscillator accross PVT corners without external components or extra trimming pins?
Is that hard to implement?
Thanks a lot!!!
Best Regards
Analog_starter
Yes, I know that paper.
But I want to know how to simulate the current mode filter. What aspect or parameter should be simulated? That very different with charge pump pll design.
Thanks a lot!
Can anybody tell me how to simulate the current mode filter? I don't know what aspect or parameter should be simulated.
and why not to replace the charge pump PLL since the CMF PLL can reduce the chip size significiantly?
Thanks a lot!
Hi all,
Could you tell me how to generator a delay and its pulse width
is independent across PVT?
Or show me some reference about ATD circuit for flash memory.
Thanks a lot !!!
Regards
Analog_starter
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