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Recent content by Alosevskoy

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    Write leveling for single dram DDR3 device

    Hi,everyone! :wink: As I understood write leveling was introduced with DDR3 memory devices to compensate ck-dqs skew caused by fly-by routing topology. My system uses only one dram device so I think there is no significant delays on ck/addr/cmd bus caused by fly-by topology. Should I still...
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    PC<->FPGA communication with udp1.0.8 Tcl extension

    PC&lt;-&gt;FPGA communication with udp1.0.8 Tcl extension I figured out what happened. PC sent arp packets because it didn't know fpga's mac. I used command (in cmd) "arp -s fpga_ip fpga_mac" to tell PC about fpga's mac.
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    PC<->FPGA communication with udp1.0.8 Tcl extension

    Hello, guys! I'm using Tcl udp extension to communicate between PC and FPGA through Ethernet. I designed transmission part (UDP/IP stack + MAC) in FPGA and tried to send udp packets from FPGA to PC. It's all Ok - I see packages on PC side using Wireshark packet analyzer with no errors. After...
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    Gated Clock: why using of Latch is preferred over using a FlipFlop

    One of the reson is that latches smaller then flip-flops.
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    how to get timing report in SYNOPSYS PRIMETIME?

    Hello! Timing report about setup times for all registers: report_timing -to [all_registers -data_pins] Timing report about hold times for all registers: report_timing -to [all_registers -data_pins] -delay_type min Timing report about setup time for a particular register (for example...
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    Importing verilog netlist to Cadence

    Pin names for vddand gnd you can see in properties window, for vdd is vdd! and for gnd is gnd!. In our standart library std cells the power and ground pins are vdd! and gnd!, so there are no problems... Sorry, but I don't know how to handle power ground pins in your case.
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    Importing verilog netlist to Cadence

    Hi! At the top level add vdd, vsource and gnd from analogLib library (see the pic). Specify in vsource the voltage you need...
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    Help needed on basic Verilog coding--"for looping"

    I think the problem is not in the clk signal... because you dont need it to simulate a pure combinational multiplier... The loop never stops because the condition is always true. Let's see.... InA = 11110, 11111, 00000, 00001.. and again, and again.... :-D (the same things actual for InB loop)...
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    VCS simulation error concerning memory (32-bit)

    May be some problems exist in your RTL or testbench. For example, $finish is never achived so it causes "infinite" time to complete simulation). // tb.v reg a; // initial block with stimulas initial begin a = 1; // forever 1 wait(a == 0); // this event will never occur, but the simulator...
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    [SOLVED] Excluding Hard Blocks from CORE size calculation

    Thank you, rca, for the quick reply! I don't need to place the hard blocks (macroses) on CORE's rows (where only std cells of Digital_Logic part should be placed). So I want to exclude the macroses sizes from CORE (row array) size calculation. Digital_Logic and macroses has different power...
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    problem in Instantiating

    (1) Instantiations are not allowed in the procedural blocks (always in this case). (2) logicresult & arithmeticresult should be the same size as result (wire [3:0] logicresult, arithmeticresult;) (3) declare logicresult & arithmeticresult in the module body (not in the port list)...
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    [SOLVED] Excluding Hard Blocks from CORE size calculation

    Hi, guys! I'm using SOC Encounter as a layout tool. I need the florplan depicted below: The problem is the tool uses hard blocks sizes while calculating CORE size. So the question is how to exclude them from CORE size calculation (it should be determined only by Digital_Logic module). The...
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    problem in verilog code

    Yes, sorry.... The final value is 2... Fix condition for the for loop, i.e for(j=7;j>=0;j=j-1). I've modeled the code and as expected it returns 2 for 8'hA4. But it's still non-synthesizable code... Do not use for loop in a software manner, think about hardware (comb logic, flip-flops, etc) when...
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    problem in verilog code

    This code is not synthesizable. Elaborate your design please (synchronous logic or pure combinational logic; function). You're sending to the module 8'hA4 = 8'h10101000... Let's follow your code. Enter to always@ block... Initial values for count and o is 0... 1 iteration of for cycle: i[7]==1...
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    problem in verilog code

    Post please the vectors you send to the module, i.e. i = 8'h....(or maybe you can attach waveforms) If the lsb of the vectors is 1 then you will always get count=0 ( your code do that: see the portion of the code where else statements take place). Are you going to synthesize this code?
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