Importing verilog netlist to Cadence

[jkbagada]

Hello friends

I have imported a synthesized Verilog netlist to Cadence for spice simulations. Now i see there are no VCC, GND pins at top level. while down at standard cell level VCC, GND pins can be seen. I tried running simulations by giving stimuli in ADE at Global sources but shows errors, moreover i dont wish to give supply by stimuli.

How do i give supply (by connecting voltage source) at the top most hierarchy?

Thank you!

 

[Alosevskoy]

Hi!
At the top level add vdd, vsource and gnd from analogLib library (see the pic). Specify in vsource the voltage you need...

 

[jkbagada]

Hi ,Thank you


This could be done but the pins at lower hierarchy (standard cell) are named VCC! and GND!, you think this will directly connect the source to those pins since global pins are named Vdd and gnd?.

 

[Alosevskoy]

Pin names for vddand gnd you can see in properties window, for vdd is vdd! and for gnd is gnd!.
In our standart library std cells the power and ground pins are vdd! and gnd!, so there are no problems...
Sorry, but I don't know how to handle power ground pins in your case.