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I did not totally understand what do you mean. On this graph, my initial idea to compute for process corner variations (TT to FF, TT to SS) is just to get the specific value at room temperature then proceed to (FF value - TT value) / TT value. However, I am perplexed if I will also include the...
Good day Sirs/Maams,
Hope you are all doing good.
Shown below are the TT,FF and SS graphs (top to bottom).
I am confused on how to properly measure the process variation of this one.
Do I need to include into consideration the range of the y-axis?
By the way, these are the TTFFSS corner graphs...
Good day friends,
I would like to ask help regarding this error from the layout.
I using TSMC 0.18um 1P6M process.
My design requires an NMOS with a shorted source and bulk.
Thank you.
hello everyone, I used a two stage OP in every LED branches shown in the figure.
From the presim, shown on the second figure, the two input terminal voltages are at*
virtual short.
However, during the post layout simulation shown on the third and the last figure,
they're not on a...
I suspect it's the parasitic resistance. In a certain block, I used the C+CC extraction type instead of the R+C+CC option. The results went well. But when I integrated the whole chip, even though I got a clean LVS. There are some block (voltage bandgap, in my case) fail.
Apparently, I consider...
I had finished doing the chip layout of the LED driver IC. The post layout simulation of each block performs well. Moreover, the whole chip layout passed the DRC as well as the LVS. But, the post layout simulation fails. I was advised to debug it from the parasitic extraction results (PEX). The...
I have only tried asking help on CIC regarding PDKs for the layout but I have never asked them about simulation tools.
Do you think CIC will provide me with the Nanosim? thanks.
Good day!
I'm having my post layout simulation now. I'm using HSpice but it would took me weeks to finish it.
I want to use Nanosim. Please share it to me where can I have one.
Hello EDA fellows,
I have some questions regarding filter design.
Hope you can have a look at this one.
Concern #1. From the diagram at the left, I have read some papers having a 0dB and -3dB passband gain. I want to ask what's the typical value for that? What could be the possible reasons...
Hello EDA fellows,
The graph below shows the post simulation using the R+C+CC and C+CC extractions.
The problem can be traceable to the parasitic resistance.
The expected result is the same as that of the C+CC.
My concern now is how to reduce the parasitic resistance in the layout.
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