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DCM is a primitive, u can instantiate it in your code. To learn how it works, read the V2 user guide chapter 3.
Once u generate the clocks(clk_SDRAM) that needed by the other components on the board(SDRAM...), just use it drive a OBUFDS, and the output of this cell will be two differential...
Hi, Echo47:
I mad a try in your "KEEP" way, it's OK. The inverters didn't been optimized.
I fonud that invoking the "generate post synthesize simulate module" will generate a netlist file(*.v), here we can see the synthesize results.
and in my try, the inverter didn't be optimized...
Thanks, Echo47!
I will make a try in your way.
and I find that maybe the Primitive IDELAY is helpful too.
To see the netlist have to wait until PAR complete?
xst (* keep = true *)
Hi, thanks for your attention.
Do you know how to keep some logic and prevent it from being optimized by the XST? For example I want to delay the clk by adding two extra NOT gate. How to KEEP the two NOT gate? And where and how to see the synthesize result to make...
Thanks for your attention.
When i do projects in ISE, sometimes for the reason of code modification or cdc change, I will rerun a project that have finished(all the process were marked by "!").
If just the cdc file is changed, then before the resun, I will not "clear the projests". Then...
I think Xilinx allways synthesize xx in statement "if (xx'event and xx = '0/1') " as a clk pin of the FlipFlop, there is only one clk pin in a FF cell. So there should not be two such statements in one process. One process one clock domain.
ise fpga
Thanks rberek.
U have list many possible causes of timing violation which is very comprehensive. But I can't modify the code, whose timng is OK when there is no CDC or only a small CDC. And I will not modify the PAR relust manually. Maybe I can try different synthesize tool and...
improve timing fpga ise
Hi, thank u for your attention.
I am doing FPGA verification with ISE. The codes are fixed. signals in CDC file will be modified.
Sometimes when the signals in CDC are too many, then after PAR, there will be timing violations. By using timing analizer and FPGA...
chipscope sample
Hi, thank u for your attention.
My work platform: Xilinx Virtex2; ISE8.2.0.3i service pack2; Chipscope : 8.2.0.3i.
My design : signals to obversed in chipscope is in clock domain CLK_a( 125mHz). and about 40 signals, little, BRAM resource is Ok.
Chipscope sample clk...
Re: Plz help me: "internal error" during MAP proce
Thank u very much! These two web pages are very useful.
Now I think I've found the cause of the problem.
Ps: Unchecking the "regiseter duplication" will worsen the timing of the result. Sometimes there will be timing violation in the PAR...
Re: Plz help me: "internal error" during MAP proce
Hi, echo47 & banjo
sorry for late acknowledge.
echo47:
"Did the errors begin right after you made a significant change to your project?"
yes.
"You mentioned a cdc file. Does it pertain to the "internal error" problem? "
and banjo: "then I...
Hi,
Now i am doing a project in ISE. In my project, there is a *.cdc file which I used to observe internal signals with chipscope later. The device I used is Vertex4.
Is there anyone encountered this problem when running ISE :
The project is successfully synthesized, then is the map...
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