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Recent content by alainsan

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    Tcp/ip stack protocol: Implementation in spartan 3e500 fpga

    An overview of IP/TCP stack implementation in FPGA can be found here: comblock.com/download/com5402soft.pdf (TCP server) comblock.com/download/com5403soft.pdf (TCP client) These run on a Spartan-6 at 125 MHz for gigabit Ethernet.
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    Help with timing simulation.

    Under view simulation, there is a (not obvious) pull-down menu whereby one can select "behavioral" or "Post-route". Select the latter.
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    How to Implement IPv4 in VHDL

    This IP/UDP/TCP/ping/ARP stack works at full speed on GbE. It runs on a low-cost Xilinx Spartan-6 with a 125 MHz processing clock. www.comblock.com/download/com5402soft.pdf
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    How to read data from an FPGA through USB

    Here's an example of FPGA development board with USB 2.0 and DDR2 memory: COM-1600 FPGA + ARM + USB 2.0 + DDR2 + NAND DEVELOPMENT PLATFORM From the schematics (https://comblock.com/download/com_1600schematics.pdf) you can see that the Xilinx Spartan-6 FPGA is connected externally to a USB PHY...
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    fpga + software radio

    Here's another pointer: ComBlock > Home > Product List > COM-3011 [20 MHz - 3 GHz] Receiver / SDR This is a new receive-only SDR covering at least 20 MHz - 3 GHz. The development environment is (a) Xilinx ISE for the FPGA [the free webpack works] and (b) Eclipse/gnu for the ARM Cortex M3...
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    Looking for UDP IP stack in VHDL

    Re: UDP IP stack in VHDL ComBlock.com will release a core that meets your requirements this month. The COM-5402SOFT TCP/UDP/IP stack core for Spartan-6 (no external RAM, standard MAC interface) is written in VHDL and includes all the source code. Speed is 1 Gbps running at 125 MHz processing...
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    Good FPGA dev kit for a student who is not a complete newbie?

    Maybe this combined Spartan-6 FPGA + 32-bit ARM processor + DDR2 + USB2 + NAND development platform could be of interest: comblock.com/com1600.html It also connects to a variety of RF boards.
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    USB 2.0 -- Anybody actually implement it using the OpenCores IP?

    You may want to have a look at https://comblock.com/download/USB2soft.pdf This core interfaces to a low-cost USB2.0 UTMI PHY.
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    FSK IP cores for Xilinx FPGAs

    Re: fpga fsk ip core FSK IP cores for Xilinx FPGAs: https://comblock.com/download/com1027soft.pdf (demodulator) https://comblock.com/download/com1028soft.pdf (modulator)
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    USB 3.0 PHY for interfacing with low-cost FPGA (Spartan-6)

    We are trying to upgrade ComBlock FPGA development boards from USB 2.0 full-speed to USB 3.0. Because these boards are centered around Xilinx Spartan-6 FPGAs, the maximum interface speed should not exceed 250-300 MHz. Can anyone point us to a USB 3.0 PHY (in production (I wish), engineering...
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    BER and E0/N0 variation for different modulation schemes

    well.. it all starts with signal power S and noise power N measurements. By definition, the noise power density N0 = N/Bn, where Bn is the noise bandwidth. The energy per symbol Es = S/B, where B is the modulation bandwidth (symbol rate) The part that changes with the modulation scheme is...
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    about driver development for USB

    Whether to use a standard Windows USB driver or develop your own depends on your application. For example, if your application is like a (low-speed) human device interface, you may want to write the FPGA-side so that it appears as a standard USB HDI device. This way, you don't have to develop...
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    interleave division multiple acess

    Re: DS_CDMA Korma, Gold sequences are generated using two linear feedback shift registers Check https://comblock.com/download/com1418.pdf on page 7 for a block diagram, and page 8 for a few commonly used Gold sequences.
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    Is it possible to do facial recognition by verilog?

    I am just curious as to the system-level requirements... gozins: what would the input signal be? a fixed picture? how many pixels? how many bits on each pixel? is there a superior algorithm which could be translated into HDL? gozouts: what are the key facial characteristics to be...
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    PLL or DLL what to use for higher frequency then clock pulse

    Re: PLL or DLL what to use for higher frequency then clock p The easiest way to create a higher frequency clock in the Spartan-3 is to use the DCM. The DCM can be configured to generate 16 MHz * M / N, where M and N are integers. Frequencies above 128 MHz can be generated on the Spartan-3 but...
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