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Hi , I am realizing a digital IF system with a FPGA and I have construct a model for it with matlab/simulink. The problem is that I don't know how to use the model to measure the performance of the system, such as dynamic range, the impact of fixed-point realization on the system performace...
verilog to schematic
Hello
I think you can have a try for the fpga advantage of Mentor or the active-hdl of aldec. These tools can import verilog or vhdl source and translate them to schematic. And you can have a try for the novas.
Maybe you can image FPGA or CPLD as a ASIC with any digital logic. You can realize any function which can be realized by digital logic. Of course , you also need to consider the IO standard that FPGA or CPLD can supply.
transition bw
Hi ,
I am confusing how to evaluate the impact of filer's ripple and transition. I guess they should have some impact on the passing signal's SNR. But I havn't found any text descript the problem elaborately. Please give your comments or recommend some text. Thanks a lot...
This have puzzled me for a long time. I know I can use cordic to get the amplitude of ta multi-tone signal from I-Q signal. But how can I convert this amplitude to spectrum energy. Please give your comments. Thanks a lot.
Best regards.
Agump
windows vhdl editor
When it comes to editor for hdl , I think Emacs is the best. There exists verilog-mode.el and vhdl-mode.el. They can complete plenty of dirty work for you. In additon to that , you can use other modes to complete lots of fantastic work, such as fold , auto-complete etc.
clock generator adjustable frequency
My project need to supply a frequency-adjustable clock to a ADC , and require the clock's jitter less than 10ps.At the same time , we need put a copy of the clock to a FPGA which receives datas from the ADC. Now I know I can use VCO controlled by PLL to get...
ddc processing gain
What do you mean about "jitter noise figure is propotional to analog Fif", I think bandpass sampling and DDC both process the same Fif and just select different sampling frequency. I am not family about the processing gain and I am about to read some reference about it. Thanks.
sampling passband signals
Thanks for your reply. I have read this article and can't understand why the aperture jitter make the bandpass sampling unusable , since the aperture jitter is determined mainly by the ADC and the sampling clock. If using the bandpass sampling , a low-speed clock can...
passband sampling
Hi,
I am engaged in a project which need to process digital IF signal. The passband sampling theory shows that when we sample a signal based on the theory, we can get the signal in the base band. But when I read some references , they show me that the digtal down...
Hi, I am engaged in a filter design and have read some books about the filter. I am now knowing that I must apply the input to the filter for some time. But I can't know where to get the time. Please give me some help , thanks.
Best regards.
Agump
Thanks for your reply. In fact , the signals to the FPGA is from a share bus , and the glitch is from multi drivers' switching. So the glitch can't be avoided. I think the glitch should exist on the beginning of the signal's transition, so it seems that I need a debounce circuit. I am not...
glitch filtering in fpgas
Hi , I am realizing a FPGA which receive signals from the interface and processing it. Since the signals from the interface can have some glitch , I need filter out them. But I don't know how to do this and can't find any documents about this. Please help me with...
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