how to filter out the glitch from the interface?

[agump]

glitch filtering in fpgas

Hi , I am realizing a FPGA which receive signals from the interface and processing it. Since the signals from the interface can have some glitch , I need filter out them. But I don't know how to do this and can't find any documents about this. Please help me with this , thank you.
Best Rgds.

 

[echo47]

Please clarify "some glitch". How wide is the glitch compared to the useful data?

What's causing the glitch? It's usually better to eliminate the glitch at its source, rather than trying to filter it out.

 

[agump]

Thanks for your reply. In fact , the signals to the FPGA is from a share bus , and the glitch is from multi drivers' switching. So the glitch can't be avoided. I think the glitch should exist on the beginning of the signal's transition, so it seems that I need a debounce circuit. I am not sure I am right.

 

[jjww110]

why multi drive cuase glitch?

 

[Jepeto]

Sample the data twice or three times for each input with DFFs connected serially
For each input, if all DFFs samples are at the same logic level - data is valid
If not, glitch occurs, or input changing its logic level - data is not valid
Of course this will delay the incoming data

 

[lambtron]

Perhaps you can sample when the glitch is not present. For example, if the glitch always occurs near the clock's rising edge then sample on the clock's falling edge instead of the rising edge.

 

[melc]

Thanks for your reply. In fact , the signals to the FPGA is from a share bus , and the glitch is from multi drivers' switching. So the glitch can't be avoided.

If you have a shared bus then you should have a CS (chip select) for all devices which is sharing the bus including the FPGA. Devices which are inoperant must be on HZ (three state or high impedance). Glitches could occure only if OE or CS are selected in a wrong way.
So your problem could be other than suggested.