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Re: set_app_var simplified_verification_mode . . . what exactly does this variable do
I've got access to the man page. However, we've seen logical bugs after using this switch. I want people to tell me if they've seen any functional bugs happen due to (under) optimization -- ay
set_app_var simplified_verification_mode . . . what exactly does this variable do?
Hello,
We've been re-adjusting our set_app_var attributes. Does anybody know what the simplified_verification_mode variable do? We saw a logic bug when this was turned on, so want to know exactly what this does...
You can do a google search for these things . . . . but here you go . . .
https://www.cadence.com/rl/Resources/datasheets/encounter_rtlcompiler.pdf
https://www.cadence.com/rl/Resources/datasheets/rtl_physical_ds.pdf
Low Power design is complex. There's a lot of steps involved, but in our...
Cadence-PKS is a 7 year old product. You need to look at RTL-Compiler (RC) and RTL-Compiler-Physical (RCP)
It has advanced Low Power capabilities. This is what we use in our company to do low power chips in the RF-GPS space.
If you talk to their AE's, they can provide an RC jumpstart kit.
-- ay
Re: Synplify Query : What is the use of "Add PR Implementation" in Synplify Pro ?
This would generate the necessary floorplan and Xilinx/Altera (depending on your target FPGA) editor files. I used synplify-pro a long time ago. I don't think you can do complete ASIC type chip finishing with it...
I agree with Rajat on the threads . . . however, Back-End teams are so isolated from Front-End teams, that each team does on understand the original source of the files. I don't attribute it to lack of knowledge, but lack of awareness (and thereby lack of concern). At the end of the day...
We have a flow setup with Cadence RTL Compiler. The command for that is
write_atpg -stil > design.stil
This can be imported into Tetramax. With Mentor, I am assuming DFT advisor can do the same thing . .
-- adam
STIL as a DFT drc file should be interchangable across all three test tools; Synopsy-Tetramax, Mentor-FastScan & Cadence Encounter-Test . . .
This is pretty well controlled by the IEEE standard of STIL. Previously, in 2006 when STIL was evolving, some interoperability issues were seen. Pretty...
If you look at the construction of a clock buffer, for most ASIC libraries, its really two inverters optimized back-to-back.
Look at the gate delays of a buffer element and the inverters elements of similar drive strengths and you will see why inverters are used.
-- adam
We implemented a new flow within our company to use Cadence NC-Sim/IES with something called Power Profiling. Along with dynamic simulation, you can also do power simulation and "watch" the power usage across pipeline stages. However, reporting average power is not possible, but if I understand...
Not really an ASIC question is it? . . .
My kid who is playing around with animations uses this software called Animation Master . . . . good for animating 3d images. Has some interesting physics functions included in it.
Otherwise, AutoCad/Autodesk has simulation packages that connects with...
Esteban,
You can set up set_input_delay and set_output_delays for your synthesis tools. For Highspeed designs, setting max/min values have had best results . . .
# Constrain the input I/O path
set_input_delay -clock clk -max 3 [all_inputs]
set_input_delay -clock clk -min 2 [all_inputs]
#...
Mr. lostinxlation! Very good suggestions. We could definitely use these hints in our CAD flows as well.
One additional suggestion to get clean and easy mapping is to maintain intermediate netlists prior to optimization from the synthesis tool. This way, you will be running 2 passes of synthesis...
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