usefull and brief toturial for cadence pks!!

[hamebaman]

hi friends,
no one has a good and brief toturial for PKS cadence??I have it's users guide,but i don't have so much time to read all of it.a step by step toturial by an example specially for low power design can be very usefull for me.
thank you.i'm here waiting for your appreciable help.

 

[Adam.Yakuvitz]

Cadence-PKS is a 7 year old product. You need to look at RTL-Compiler (RC) and RTL-Compiler-Physical (RCP)
It has advanced Low Power capabilities. This is what we use in our company to do low power chips in the RF-GPS space.

If you talk to their AE's, they can provide an RC jumpstart kit.
-- ay

 

[hamebaman]

you mean RTL-Compiler (RC) and RTL-Compiler-Physical (RCP) are different softwares from cadence-PKS??would you give me a link??
my friend,it seems you are a chip designer,would you tell me you work on which part of RF-GPS chip??i'm working on a system on chip for zigbee,specially on digital parts and i have some problems that only an expirienced one can help me!

 

[Adam.Yakuvitz]

You can do a google search for these things . . . . but here you go . . .

https://www.cadence.com/rl/Resources/datasheets/encounter_rtlcompiler.pdf
https://www.cadence.com/rl/Resources/datasheets/rtl_physical_ds.pdf

Low Power design is complex. There's a lot of steps involved, but in our evaluation, Cadence tools are most advanced for Low Power solutions . . Here are the steps

1. Identify the user needs (surfing, cell-phone, zigbee etc., GPS, demographic, switched off most of the time)
2. Create the Low Power Architecture (Power Shut-off (w/wo retention), Multi-supply voltage, etc - clock gating etc. are all standard today)
3. Create the Low Power Specification Format (CPF and/or UPF)
4. Validate your CPF and RTL with Conformal-Low Power (CLP)
4. Import the CPF and RTL into Encounter RTL-Compiler
5. Synthesize the netlist
6. Validate the netlist Conformal-Low Power (CLP)
7. Simulate the RTL and the CPF with Incisive Enterprise Simulator (IES)
7. Import your netlist into your P&R tool (we use SoC-Encounter and Magma)
8. Plan your power structure and do place and route
9. Output a physical netlist
10. Validate your netlist with Conformal-Low Power

Good luck!
-- adam

 

[hamebaman]

woooow,thank you adam,i'm very very greatful of you,specially for giving many keywords that i needed.you cost me as mush as a diamond now,a well-exprienced engineer.i hope you i don't make you bored by my questions and not make u run away of me.
adam,please please would you introduce me a document or reference that have some examples of the design flow you mentioned above,from your projects or anything else??
and another question,i use verilog to design,as you said i can deduce that i should write my codes more structural rather than behavioral as much as i can,do you confirm??or a good software can synthesize behavioral codes to down levels very well??
thank you again very much.
---------sam