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Recent content by abhinavpr

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    ASYNCHRONOUS FIFO ISSUE: using Dual port RAM vs Flip Flops as FIFO MEMORY

    Hi , is using Flip flops as FIFO memory in an ASYNCHRONOUS FIFO a standard practice in the industry?. For smaller fifo sizes like 8-16 depths fifo inferred memory should be used. but flop inferred memory will have non registered output and that would result in getting the read data in the...
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    Asynchronous FIFO vs Multi cycle path (MCP) clock domain crossing

    Hi, Can anybody tell me the advantages of using Asynchronous FIFO when we can do the clock domain crossing using multicycle path cdc (synchronizing control enable signal and holding the input data for mulitple cycles ). why go for the pains of creating a fifo and verifying it also adding...
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    gate count cominationational vs sequential design

    Hi, i am always confused whether to go for combinatorial design or sequential design. there are always tradeoffs between different parameters and area is one of the most important of them all. can anybody tell me what guidelines to follow while designing rtl to reduce area of the ckt. we...
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    AXI master and slave design

    Hi ads-ee thanks for the code. what i meant to say was i could not find any source document for the design and it is very hard to understand. it will be really helpful if you could provide related docs.
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    AXI master and slave design

    Hi ads-ee i could not find anything at the mentioned link. can you provide the source material
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    AXI master and slave design

    Hi, i am trying to learn AXI protocol. i have gone through the spec but it didnt help that much. tried looking for master slave code on open cores but nothing is there. without the code, signals like awlock and awcache is very hard to understand if anybody has master or slave code for...
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    Disadvantages of pipelining

    Hi, more often then not i end up writing verilog code which doesn't satisfy timing closure due to long combinatorial paths and i invariable introduce pipelining. i get that it increases latency. are there any other disadvantages of introducing pipelining and what care should be taken...
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    why AWID signal is there when WID is removed from AXI4

    can anyone explain why AWID signal is there when WID is removed from AXI4. The explanation given is that AXI4 does not support write interleaving. 1. so if the write data has to be written in the order in which it arrives the whats the use of AWID? 2. in a scenario where a slave receives...
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    Empty flag generation issue in asynchronous fifo

    Hi, I have designed an Async FIFO. write clk = 50 Mhz read clk = 10 Mhz FULL flag is gnerated in wclk domain with synchronized read ptr. FULL detection in immediate. EMPTY flag is generated in rclk domain with synchronized write ptr. here EMPTY condition is not immediate as the...
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    Sampling a multibit signal at clock domain crossing

    thnks for your reply. i came across MUX-D synchrozing technique for multibit clock domain crossing. is it a recommended design practise? in mux-d synchronizer only a control signal indicating change in data is synchronized and the data is sampled at this point. i have attached the diagram...
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    Sampling a multibit signal at clock domain crossing

    Hi, i have to sample a 16bit data bus at 50 MHz into a 300 Mhz domain. as the reading is faster than writing, should i use a FIFO for this? what would be the FIFO depth? or should i simply sample the data bus every 6 clk cycles in 300 MHz domain and use 16 2-stage...
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    ASYNC OR SYNC RESET? which one is use more in ASIC industry?

    thanks everybody for the replies. it seems that asynchronous resets are more common in ASIC designs but it is still unclear whether only async resetable flops are used or both async and sync resets are used in design. like in my company async flops for control path and sync reset flops for...
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    ASYNC OR SYNC RESET? which one is use more in ASIC industry?

    how do you deal with glitches in async resets? in sync reset , a glitch can only affect it if it happens close to clock edge but in async reset any glitch can assert reset which can be really dangerous. how can you make sure that a glitch will not affect ongoing process? "Resetting all FFs is a...
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    ASYNC OR SYNC RESET? which one is use more in ASIC industry?

    Hi, i have recently moved from FPGA to ASIC and have realised that most of the ASIC designs in my new company use asynchronous reset. I find this quite different from what is generally done in FPGA. In FPGA synchronous reset designs are recommended by the vendors (xilinx/altera) as they...
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    I2C/ SMBUS slave design

    Hi, i am designing an I2C slave module . the spec says data on SDA can only change when SCL is low. can somebody tell me how to achieve that . for write operation its easy as we can sample SDA at rising edge of SCL as the data is stable before SCL rising edge but how do we write into...
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