gate count cominationational vs sequential design

[abhinavpr]

Hi,
i am always confused whether to go for combinatorial design or sequential design. there are always tradeoffs between different parameters and area is one of the most important of them all.

can anybody tell me what guidelines to follow while designing rtl to reduce area of the ckt.
we can always get the gate count after synthesis but before that while writing RTL how to figure out which design would be area efficient.

for example while designing a state machine we can go for binary encoding or one hot encoding.
one hot has timing benifits
but what about area?
for a small no. of states arnd 25 which would be more efficient one hot or binary?
one hot will involve 25 ffs and binary will have 6 but binary will also have decoder logic(comb)

in terms of gate count which will be more efficient?

 

[FvM]

in terms of gate count which will be more efficient?

It sounds like the question can be best answered by an experiment (synthesizing the circuit with different state encoding and comparing the results). Any reason not to go for a test?

 

[rahul.achates]

If you are clear about the hardware , your design will be optimized design. The only thing you will left to tool to do the logic optimizztion of your optimized design.

For Gate count, what to use / what not to use, .. its all depend on requirement. If you are working at high frequency , you might have to put more flops .. but is technology is 28 or 20 compared to 65 .. then you might be using less flops .. so it all depend on where your design will going to synthesize .. depend on that you can write RTL efficiently.

 

[D.A.(Tony)Stewart]

3:8 decoder uses 7 gates and 6 inverters
D FF uses 4 TGs , 4 gates 4 invert.

You do the math.