1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    86,815
Page 101 of 716 FirstFirst ... 51 91 99 100 101 102 103 111 151 201 601 ... LastLast
Threads 3001 to 3030 of 21460

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: IBIS Model request urgent

    Started by george_franksin, 7th May 2014 07:07
    • Replies: 3
    • Views: 597
    12th May 2014, 05:32 Go to last post
  2. Closed: designing a delay circuit using cmos logic

    Started by bunty_22, 11th May 2014 15:37
    • Replies: 4
    • Views: 513
    11th May 2014, 19:04 Go to last post
  3. Closed: ethernet hardware design W5300

    Started by asadi.siyavash, 9th May 2014 14:14
    • Replies: 11
    • Views: 1,485
    FvM
    11th May 2014, 12:22 Go to last post
  4. Closed: Trouble with loading text files into matlab

    Started by y.ettefagh, 11th May 2014 09:08
    • Replies: 0
    • Views: 427
    11th May 2014, 09:08 Go to last post
  5. [SOLVED]Closed: unexpected IDENTIFIER error , VHDL

    Started by emmagood, 8th May 2014 08:00
    • Replies: 6
    • Views: 1,266
    10th May 2014, 17:32 Go to last post
  6. Closed: Virtex 5 PS/2 keyboard

    Started by anuragmarwah, 6th May 2014 14:30
    • Replies: 2
    • Views: 523
    10th May 2014, 06:58 Go to last post
    • Replies: 2
    • Views: 542
    10th May 2014, 00:23 Go to last post
  7. Closed: Verilog/SystemVerilog ForLoop 7Segment Display

    Started by Mavnus04, 9th May 2014 20:02
    • Replies: 1
    • Views: 849
    10th May 2014, 00:14 Go to last post
  8. [SOLVED]Closed: override default generic value in HDL Designer tool

    Started by rakeshk.r, 9th May 2014 10:10
    • Replies: 1
    • Views: 1,274
    9th May 2014, 10:27 Go to last post
  9. Closed: Routing of resets in fpga

    Started by kommu4946, 6th May 2014 09:11
    • Replies: 13
    • Views: 1,153
    9th May 2014, 09:35 Go to last post
  10. Closed: How to reduce combinational node in FPGA design?

    Started by hoheiho, 7th May 2014 09:02
    • Replies: 7
    • Views: 1,769
    8th May 2014, 18:51 Go to last post
  11. Closed: Generate mamping for verilog HDL

    Started by rajavel.rv, 8th May 2014 15:29
    • Replies: 1
    • Views: 363
    8th May 2014, 17:31 Go to last post
  12. Closed: IOSTANDARD for IOBUFDS error

    Started by Shriharsha, 8th May 2014 12:00
    • Replies: 2
    • Views: 1,119
    8th May 2014, 16:02 Go to last post
  13. Closed: how do i write a dual port memory code in vhdl?

    Started by nmg, 4th May 2014 09:23
    • Replies: 17
    • Views: 1,258
    nmg
    8th May 2014, 12:41 Go to last post
  14. Closed: Wallace tree multiplier in Verilog

    Started by massive, 5th October 2003 02:06
    • Replies: 3
    • Views: 7,718
    8th May 2014, 11:24 Go to last post
  15. [SOLVED]Closed: Unable to run clock based circuits on spartan 3 fpga kit

    Started by emmagood, 3rd May 2014 10:49
    • Replies: 3
    • Views: 588
    8th May 2014, 08:08 Go to last post
  16. Closed: Parameter array in Verilog

    Started by mwn1, 7th May 2014 03:42
    • Replies: 4
    • Views: 1,066
    8th May 2014, 04:28 Go to last post
  17. Closed: FPGA from / to PC Data communication

    Started by isamel85, 7th May 2014 17:48
    • Replies: 1
    • Views: 490
    7th May 2014, 20:14 Go to last post
  18. Closed: FPGA-final implementation XIlinx ISE

    Started by graphene, 7th May 2014 17:15
    • Replies: 1
    • Views: 453
    7th May 2014, 17:31 Go to last post
  19. Closed: How to simulate an IBIS file in Orcad?

    Started by msdarvishi, 5th May 2014 21:09
    • Replies: 2
    • Views: 981
    7th May 2014, 15:39 Go to last post
    • Replies: 1
    • Views: 845
    7th May 2014, 15:35 Go to last post
  20. Closed: Xilinx ISE 14.8 Released

    Started by Zerox100, 7th May 2014 11:21
    • Replies: 3
    • Views: 1,744
    7th May 2014, 15:13 Go to last post
    • Replies: 6
    • Views: 652
    7th May 2014, 14:29 Go to last post
  21. Closed: Need Verilog/Code for Router

    Started by nvanjali, 7th May 2014 12:15
    • Replies: 0
    • Views: 761
    7th May 2014, 12:15 Go to last post
    • Replies: 2
    • Views: 565
    7th May 2014, 11:01 Go to last post
  22. Closed: How to import Date and Time from PC to VHDL codes?

    Started by Port Map, 4th September 2013 10:03
    • Replies: 10
    • Views: 1,747
    7th May 2014, 06:50 Go to last post
  23. Closed: DSP48E1-Slice Virtex-6

    Started by SharpWeapon, 5th May 2014 23:53
    • Replies: 10
    • Views: 932
    7th May 2014, 00:06 Go to last post
  24. [SOLVED]Closed: Spartan-3 External pinning on the FPGA

    Started by graphene, 5th May 2014 11:09
    • Replies: 2
    • Views: 541
    6th May 2014, 13:18 Go to last post
  25. [SOLVED]Closed: understanding memory choice in fpga design

    Started by rakeshk.r, 6th May 2014 09:56
    • Replies: 2
    • Views: 435
    6th May 2014, 11:05 Go to last post
  26. Closed: Multi-dimensional array in VHDL

    Started by gnudaemon, 19th January 2005 11:54
    • Replies: 17
    • Views: 94,630
    6th May 2014, 08:45 Go to last post

Page 101 of 716 FirstFirst ... 51 91 99 100 101 102 103 111 151 201 601 ... LastLast