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Threads 3001 to 3030 of 21629

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Writing file on FAT32 flash memory with USB Host?

    Started by Port Map, 27th June 2014 09:45
    • Replies: 0
    • Views: 511
    27th June 2014, 09:45 Go to last post
  2. Closed: how to decode/emcode and compress/decompress NTSC/PAL video?

    Started by Port Map, 26th June 2014 16:02
    • Replies: 5
    • Views: 614
    27th June 2014, 08:53 Go to last post
  3. Closed: Detecting the beginning of the JTAG programming

    Started by Binome, 26th June 2014 09:25
    • Replies: 2
    • Views: 380
    27th June 2014, 08:35 Go to last post
  4. Closed: Ethernt to USB Adapter Using FPGA

    Started by amirdiani, 25th June 2014 05:53
    • Replies: 2
    • Views: 460
    27th June 2014, 02:08 Go to last post
  5. Closed: Camera interfacing with Virtex5 FPGA

    Started by poonampawar189, 26th June 2014 07:03
    • Replies: 1
    • Views: 466
    26th June 2014, 21:10 Go to last post
  6. Closed: words per minute confusion

    Started by Bhuvanesh123, 26th June 2014 12:50
    • Replies: 3
    • Views: 401
    26th June 2014, 18:45 Go to last post
  7. Closed: Noise that affect the channel

    Started by Bhuvanesh123, 26th June 2014 12:35
    • Replies: 1
    • Views: 371
    26th June 2014, 17:23 Go to last post
  8. Closed: Place & Route takes too long

    Started by SharpWeapon, 25th June 2014 18:10
    • Replies: 15
    • Views: 999
    26th June 2014, 17:07 Go to last post
  9. Closed: verilog code for 8-bit array multiplier

    Started by Mohammed Yameen Musharruf, 24th March 2014 15:37
    • Replies: 3
    • Views: 9,891
    26th June 2014, 16:21 Go to last post
  10. Closed: how to write verilog code for QPSK modulation?

    Started by firephenix405, 23rd July 2009 19:39
    • Replies: 8
    • Views: 6,064
    25th June 2014, 20:11 Go to last post
  11. Closed: real time video processing in FPGA xilinx virtex 5

    Started by zahra.asl, 2nd April 2013 10:28
    • Replies: 5
    • Views: 934
    25th June 2014, 17:39 Go to last post
  12. Closed: Batch file for ISE 9.2 not running

    Started by verylsi, 25th June 2014 09:38
    • Replies: 3
    • Views: 701
    25th June 2014, 16:21 Go to last post
    • Replies: 4
    • Views: 784
    25th June 2014, 07:15 Go to last post
  13. Closed: Metastability and synchronizers

    Started by bsbs, 19th June 2014 06:10
    • Replies: 5
    • Views: 1,144
    25th June 2014, 06:57 Go to last post
  14. Closed: FSM Based Controller

    Started by malikkhaled, 24th June 2014 13:41
    • Replies: 3
    • Views: 448
    24th June 2014, 16:51 Go to last post
  15. Closed: error with restoring division

    Started by shaiko, 24th June 2014 10:22
    • Replies: 7
    • Views: 596
    24th June 2014, 14:46 Go to last post
  16. Closed: Connecting modules in VHDL

    Started by graphene, 23rd June 2014 17:46
    • Replies: 4
    • Views: 1,456
    24th June 2014, 10:58 Go to last post
  17. Closed: ROHC CRC Calculation

    Started by rajavel.rv, 21st June 2014 05:22
    • Replies: 2
    • Views: 1,098
    24th June 2014, 07:13 Go to last post
  18. Closed: VHDL twos complement to decimal conversion

    Started by graphene, 19th June 2014 11:48
    • Replies: 12
    • Views: 5,758
    23rd June 2014, 17:49 Go to last post
  19. Closed: 8 bit Shift Left Logical Implementation code

    Started by haidar123, 23rd June 2014 14:08
    • Replies: 2
    • Views: 742
    23rd June 2014, 16:51 Go to last post
  20. Closed: Using unconstained input ports in VHDL 2008

    Started by shaiko, 23rd June 2014 11:16
    • Replies: 5
    • Views: 876
    23rd June 2014, 15:05 Go to last post
  21. Closed: Declaring an unconstraind varaible inside a function

    Started by shaiko, 23rd June 2014 10:00
    • Replies: 4
    • Views: 695
    23rd June 2014, 14:56 Go to last post
  22. Closed: Problem to configure xilinx virtex2pro board PHY LXT972A(U12)

    Started by varun_agr, 23rd June 2014 06:59
    • Replies: 0
    • Views: 405
    23rd June 2014, 06:59 Go to last post
  23. Closed: open source PLB to AMBA AHB bridge

    Started by manno, 22nd June 2014 14:27
    • Replies: 0
    • Views: 439
    22nd June 2014, 14:27 Go to last post
  24. Closed: Multicore Leon3 without OS

    Started by Makni, 21st June 2014 17:17
    • Replies: 1
    • Views: 493
    22nd June 2014, 00:15 Go to last post
  25. Closed: FM Modulator/Demodulator Using Verilog on FPGA

    Started by shahinjc, 13th June 2014 19:51
    • Replies: 4
    • Views: 1,111
    21st June 2014, 09:53 Go to last post
  26. Closed: hopping code receiver problem with pic16f876a

    Started by yaser222, 20th June 2014 09:46
    • Replies: 0
    • Views: 491
    20th June 2014, 09:46 Go to last post
  27. Closed: low density parity check

    Started by bunty_22, 19th June 2014 17:14
    • Replies: 1
    • Views: 525
    19th June 2014, 17:28 Go to last post
  28. Closed: UART help... My UART is not working..

    Started by Waqar Rashid, 19th June 2014 11:49
    • Replies: 1
    • Views: 579
    19th June 2014, 13:12 Go to last post
  29. Closed: ISE 14.7 & Matlab 2014

    Started by shazdek0ch0l0, 14th June 2014 18:08
    • Replies: 4
    • Views: 1,728
    19th June 2014, 07:49 Go to last post