1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    92,955
Page 101 of 725 FirstFirst ... 51 91 99 100 101 102 103 111 151 201 601 ... LastLast
Threads 3001 to 3030 of 21746

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: simple logic circuit related question

    Started by sudarshann, 28th July 2014 20:04
    • Replies: 3
    • Views: 539
    28th July 2014, 21:45 Go to last post
  2. Closed: Need some Advice in VHDL

    Started by Adnan86, 27th July 2014 19:06
    • Replies: 17
    • Views: 824
    28th July 2014, 20:15 Go to last post
  3. Closed: Synthesizer selected unintended Qual port RAM

    Started by SharpWeapon, 28th July 2014 16:36
    • Replies: 8
    • Views: 539
    28th July 2014, 20:06 Go to last post
  4. Closed: Requires help for my first project.

    Started by Y.SAI SARASWATHI, 27th July 2014 12:54
    • Replies: 2
    • Views: 488
    28th July 2014, 18:49 Go to last post
  5. Closed: reduce number of flip flop

    Started by siasia, 28th July 2014 15:03
    • Replies: 3
    • Views: 560
    28th July 2014, 16:37 Go to last post
  6. Closed: Scope of variables and signals in VHDL and Verilog

    Started by Dijskstra, 27th July 2014 16:59
    • Replies: 2
    • Views: 1,389
    28th July 2014, 15:58 Go to last post
  7. Closed: What does Burst Mode......Burst Transfer...refers to?

    Started by Guru59, 15th March 2007 13:07
    • Replies: 6
    • Views: 6,805
    28th July 2014, 11:49 Go to last post
  8. Closed: Looking for timing diagram tool for drawing the waveform signals

    Started by rvkei11, 21st April 2010 09:31
    • Replies: 6
    • Views: 27,006
    27th July 2014, 20:37 Go to last post
  9. Closed: fpga based motor project

    Started by minusundar, 18th July 2014 06:14
    • Replies: 4
    • Views: 697
    27th July 2014, 18:40 Go to last post
  10. Closed: Regarding VMEbus BASICS

    Started by sagar.bavane, 8th August 2013 11:26
    • Replies: 3
    • Views: 590
    26th July 2014, 18:35 Go to last post
  11. Closed: Help for VHDL code, definition of matrix 2D

    Started by Adnan86, 25th July 2014 21:14
    • Replies: 10
    • Views: 769
    26th July 2014, 16:12 Go to last post
  12. Closed: [Moved] project msic vectors using xilinx xpower analyzer

    Started by gnseeta.btech, 26th July 2014 07:46
    • Replies: 0
    • Views: 448
    26th July 2014, 07:46 Go to last post
  13. Closed: Frontend vlsi opening

    Started by alokkmr18, 25th July 2014 12:10
    • Replies: 1
    • Views: 497
    25th July 2014, 18:52 Go to last post
  14. Closed: Problem with the design of a SPI Master in VHDL

    Started by mrbigglio, 24th July 2014 00:17
    • Replies: 11
    • Views: 1,421
    25th July 2014, 17:30 Go to last post
  15. Closed: [Moved] verilog code for LZ78 algorithm

    Started by Ashok_Pacha, 23rd July 2014 11:35
    • Replies: 3
    • Views: 750
    24th July 2014, 02:33 Go to last post
    • Replies: 7
    • Views: 1,099
    23rd July 2014, 21:31 Go to last post
  16. Closed: Help for VHDL code, wrong answer

    Started by Adnan86, 22nd July 2014 16:29
    2 Pages
    1 2
    • Replies: 23
    • Views: 1,660
    23rd July 2014, 20:51 Go to last post
  17. Closed: What is Emulation work in Industrty?

    Started by jay496, 23rd July 2014 12:37
    • Replies: 5
    • Views: 539
    23rd July 2014, 15:48 Go to last post
  18. Closed: [Moved] what is bit- true implementation

    Started by preethi19, 22nd July 2014 05:12
    • Replies: 4
    • Views: 1,874
    23rd July 2014, 13:14 Go to last post
    • Replies: 4
    • Views: 702
    23rd July 2014, 02:04 Go to last post
  19. Closed: Mamdani Fuzzy Inference System in FPGA

    Started by nami31, 23rd July 2014 01:40
    • Replies: 0
    • Views: 503
    23rd July 2014, 01:40 Go to last post
  20. Closed: How to use Altera cyclone and VGA monitor ?

    Started by bianchi77, 22nd July 2014 23:27
    • Replies: 1
    • Views: 595
    23rd July 2014, 01:25 Go to last post
  21. Closed: Problem when simulating a register

    Started by Binome, 17th July 2014 10:21
    • Replies: 11
    • Views: 658
    22nd July 2014, 14:10 Go to last post
  22. Closed: 2D-Array Write into a file

    Started by sresam89, 17th July 2014 00:50
    • Replies: 3
    • Views: 557
    22nd July 2014, 14:09 Go to last post
  23. Closed: altera fir compiler channel manage

    Started by franticEB, 22nd July 2014 10:02
    • Replies: 3
    • Views: 594
    22nd July 2014, 14:08 Go to last post
  24. Closed: incrementing unsigned array

    Started by shaiko, 27th June 2014 15:52
    • Replies: 5
    • Views: 532
    21st July 2014, 22:50 Go to last post
  25. Closed: revolution counter for motor

    Started by kranthi_vlsi, 21st July 2014 13:52
    • Replies: 1
    • Views: 475
    21st July 2014, 18:17 Go to last post
  26. Closed: costnat value for whole matrix in VHDL

    Started by Adnan86, 20th July 2014 21:41
    • Replies: 11
    • Views: 696
    21st July 2014, 16:15 Go to last post
    • Replies: 6
    • Views: 628
    21st July 2014, 16:13 Go to last post