Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

zq calibration of ddr3l

Status
Not open for further replies.
A

Akshata G M

Newbie level 3
Joined
Jul 2, 2013
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
16
Dear all,
We are doing a project on DDR3L IO, can anyone tel me what is the logic behind pull up and pull down ckt in zq calibration.
SAR logic is needed for counter or Can we use common counter counting from 0 to 15 for pcode and ncode counter.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top