Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

zero cross pulse circuit sometimes goes wrong

cupoftea

Advanced Member level 5
Joined
Jun 13, 2021
Messages
2,788
Helped
55
Reputation
110
Reaction score
120
Trophy points
63
Activity points
14,735
Hi,

We have a zero cross detector , one on each phase to phase, for a 3 phase delta supply. We are just operating it with one singe 60Hz phase (85-125vac) at the moment. We are using a single phase AC power source. (with settable frequency and amplitude, etc)

The ZCD is a very common one that I have seen before, but I can’t show it here. It is all discrete, using BJTs, diodes, Zener, res and caps.

It gives a zero cross pulse just before the zero cross.

On our other product, the 3 phase star 240VAC phase system, this zero cross detector seems to operate fine, giving a pulse some 400us away from the zero cross.

But when we put in the single phase input at 85-125vac, in the 3 phase delta product, it sometimes goes wrong. The expected (acceptable) operation, which we usually see, involves the rising edge of the zero cross pulse getting nearer to the zero cross as the mains is increased from 85vac to 125vac. This is also the operation that the simulator shows for it. However, sometimes a particular channel will show the reverse of this, ie, the zero cross pulse getting further from the mains zero cross as the mains is incremented from 85vac to 125vac. Also, the rising edge of the zero cross pulse ends up too far from the zero cross when at 125vac (about 600us instead of 300-400us).

So anyway, sometimes the circuit works properly, and sometimes not. On the 240VAC 3 phase star system, we haven’t yet seen it go wrong on that.

We are thinking its possibly one of the following…

1…Something to do with the diff probes leakage current to earth.
2…Something to do with the single phase AC power source
3…Something to do with the input common mode choke , in that with just one phase into it, it will show more inductance, and there is ringing at the zero cross which affects the zero cross detector.


Do you have experience of the same problem?, a zero cross pulse sometimes going wrong like this?
 
Sorry i cant, ..though all the discrete ones are all much of a muchness as you know. I am thinking others will have had this problem with theirs too.
 
The circuit has a 400V, 10nF film capacitor in it. If that capacitance gets higher in capacitance with the higher mains, then that causes this issue......i wonder if this is the case?...its a 400V capacitor and it has at the most, 51V peak on it......so i wonder if this guilty capacitor is actually not the 10nF that we think it is...and actually it increases its capacitance when at 125vac, it has the slightly higher voltage on it...?

Actually, this guilty suspect 400V film capacitor has 38vpk on it when at 85vac, and 46vpk on it when at 100vac, and 52vpk on it when at 125VAC....i winder if this is just too little voltage for this capacitor?
 
3 phase delta

Simulation of 3-phase. Delta configuration. 6 led's light to indicate direction of current.

Dots next to generators confirm all 3 in correct orientation. Scope traces confirm correct sequence of waveforms (positive and negative portions).

To create normal operation for the led's I set source V approximately but not identically 2.5V amplitude (even though it's abnormal level in real systems).

All 6 led's light when you expect them to. However notice current doesn't always flow in expected direction through generators. This is happening because it's low voltage and low current. I don't see it when I simulate hundreds of V, current draw several Amperes. But it might turn up where delta configuration is not exactly balanced.

3-phase delta shape 6 led's indicate all current directions.png

--- Updated ---

Click link to:

1) Navigate to falstad.com/circuit,
2) Load my schematic into animated simulator,
3) Run it on your computer.


Toggle full screen (under File menu).
Enlarge scope trace height by dragging upward at top of scope region.
 
Last edited:
The ZCD is a very common. It is all discrete, using BJTs, diodes, Zener, res and caps.

It gives a zero cross pulse just before the zero cross.
For triggering a Triac, ensure the pulse exists after the zero-crossing.
 
Changing voltage changes the signal to the ZCD and so is
likely to change its delay. Unclear whether the "wrong" yip
is a different circuit board, if so look to component or
build oddities I guess. Put normal and abnormal in lock step
and cross probe.
 
The circuit has a 400V, 10nF film capacitor in it. If that capacitance gets higher in capacitance with the higher mains, then that causes this issue......i wonder if this is the case?
You're on the wrong track. Film capacitors are highly linear and have no relevant voltage dependency.
 
For triggering a Triac, ensure the pulse exists after the zero-crossing.
Thanks, the actual triggering is done via the micro, which reads the zx pulse, and then does some processing etc.
You're on the wrong track. Film capacitors are highly linear and have no relevant voltage dependency.
Thanks, and i know what you mean, but this cap is required to give the phase lead of the zx pulse from the actual zx.....and we want the pulse 300us leading the zx.....when at 125vac, and 300us away from the zx, the mains voltage is at just 16V...it seems implausible that a 400V rated 10nF cap could still be 10nF with just 16V on it?

We havent seen the problem at 240VAC...but that gets a shot of higher voltage to it at the peak of each mains half cycle...and i believe, that kind of invigorates it to still have the same capacitance when at the zero cross....kind of the "Memory" effect.
 
Last edited:
.it seems implausible that a 400V rated 10nF cap could still be 10nF with just 16V on it?
Why should it be implausible?
As FvM pointed out film capacitors don't change (much) capacity with applied voltage.
(In opposite to ceramics capacitors)

Klaus
 
Thanks, i actually wonder if a slight bit of moisture has got into the capacitor, and that at low voltages, this is having the effect of changing its capacitance at low voltages. Or maybe the capacitor is just old, and its chemistry has changed such that at low voltages it appears to loose capacitance?
 
Board flux residue can also be a variable when using high value
resistors. More of a thing for lab-bodge boards than production
where a flux-clean step would be part of the plan.
 
Last edited:
This seems to indicate there is a V dependence albeit small, but not zero
The paper doesn't measure an actual voltage dependency of film capacitors. It shows a THD+N curve which is effectively (within limits of uncertainty) equal to specified floor of the ADC itself. Clearly inappropriate to determine distortions caused by film capacitors, except saying it's < xx dB. Would be at least sufficient to validate the claimed irrelevance of capacitor voltage dependency for the discussed application.

A relevant deviation from ideal behaviour of film capacitors in some application is their loss factor. It matters e.g. in precise integrators, it's usually the limiting factor for integrating ADC like classical dual slope type. But still orders of magnitude below a value that matters for the discussed application.
 
Yes, it is. In the meaning of usefulness or common sense.

because "zero" in the analog world basically does not exist. So when we speak about zero, then we always mean "close to zero".
Example: you may use a (digital) microcontroller and do a mathematical "compare" of two numbers.

IF ( A == B) ...

and the result may become true. It may stay true for a period of time.

But do the same in an analog world:

IF (temperatureB == temperatureB) ... (or time, or weight, or length...)

it will never become true.
Maybe you more like this definition: the time for it to be true is 1/infinite .. which more or less is zero.

Coming back to digital: There is a step size aka resolution, a value with allowed tolerance.
Often +/- 0.5 LSB. And if you designed yur system correctly this tolerance should not affect operation.

Let´s apply the same to the analog world. If the "change" is small enough to have no affect to the proper operation, then let´s call it zero.
*****
I guess the question was somehow meant as a game ...

There always is a change. Change with time, change with temperature, change with humidity, change with everything.
There is no true "zero drift" OPAMP, no zero delay, no Rail-to-rail (zero offset to rail), no zero bias current ....


Klaus
 
The paper doesn't measure an actual voltage dependency of film capacitors. It shows a THD+N curve which is effectively (within limits of uncertainty) equal to specified floor of the ADC itself. Clearly inappropriate to determine distortions caused by film capacitors, except saying it's < xx dB. Would be at least sufficient to validate the claimed irrelevance of capacitor voltage dependency for the discussed application.

A relevant deviation from ideal behaviour of film capacitors in some application is their loss factor. It matters e.g. in precise integrators, it's usually the limiting factor for integrating ADC like classical dual slope type. But still orders of magnitude below a value that matters for the discussed application.
Ah yes capacitor soakage :


Yes the paper did not do analytical measurements. In fact searching web, and IEEE docs, I do see
a paper done film V versus T changes due to AC V......but cannot get a copy of it (so far, usually I
contact authors and they provide).

Regards, Dana.
 
Is it strictly correct to say film C caps dont change their value with V, yet they do
with T, and if V changes does not the T change due to dissipation in the ESR ?
1698154769205.png


This seems to indicate there is a V dependence albeit small, but not zero -

Regards, Dana.
For a 1st order thermal rise and 2nd order voltage rise with power dissipation given some linear lossy resistance = V/I, we might expect some 2nd order effect with temperature.

Yet PET & PEN poly. mat'ls are 3rd order and PPS & PP are -1 order effect with temperature ['C].
 
given their performance is better than +/- 2% in the above graphs, and knowing something of the dielectric, poly prop caps have very minimal change in value with applied volts - although as you run nearer to full volts - there are additional losses due to dielectric stress [a type of hysteresis loss ] and I^2R losses go up - as higher volts also means higher currents - so the temp goes up and then the above graphs apply ).
 

LaTeX Commands Quick-Menu:

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top