Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Z- high impedance VALUE

Status
Not open for further replies.

sprinto

Newbie level 3
Joined
Dec 16, 2008
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,315
high impedance value

Suppose V(high)=1.5v for logic 1 and V(low)=0v for logic 0 . Generally what should be the voltage value of Z-HIGH IMPEDANCE state?.

To elaborate,
In bi-directional IO operations we usually make use of this Z state(using GZ pin) . Z state is used to transmit no LOGIC. But how is this done?. Is it completely disabling/disconnecting the port or making it to reach a voltage value which does not imply any logic.
 

typical high impedance values

In a high impedance state the value would generally be undetermined.

Example: If you are using a CMOS inverter and both the NMOS and PMOS are off, then the output can be anywhere from Vdd to Vss.
If you were to connect a pull up and pull down resistor (of equal value) at the output then it will be half Vdd-Vss.

In high impedance in your I/O port, it probably disabling the path completely so it does not interfere with the signal. Example: switch off your transmission gate so that no signal flows.
 

high impedance logic value

Thanks for the reply.

I was getting a voltage level of 1.5v when GZ is active. As you have explained I think its the voltage value betweem Vdd -Vss (1.5 to 0).

My spec doc says for GZ condition its 1.65v always. Which seems like it is determinable.
1. Any idea why I am getting always 1.5v?.

In my spec doc, I see two combination on voltage supplies.
a)Vdd=1.5 Vss=0.
b)Vdds=3.3 Vsss=0

2. why they use different combination of supplies?.

3. I was expecting Vss to be higher value than 0(compared to GND), but both Vss & Vsss are at 0v. Why?
 

how to determine pin is high impedance

GZ does not necessary be between Vdd -Vss depending on your circuit topology.
Try connecting pull up and pull down resistor at your output and measure the output voltage.

15_1229486268.jpg


High impedance state may just be for the output path of the I/O pin. The output of the I/O pin itself maybe at a different state.

1. I have no idea why it is 1.65V. Check to see if there are additional condition stated in your spec doc to obtain 1.65V
Note: the output of your circuit should not be higher than your supply voltage unless u step up your voltage internally (ex:charge pump)

2. Vdds=3.3 Vsss=0
=> is for substrate/ guadring (i can't help you on this)

3.Vss can be higher than ground but it is usually grounded. Since your Vdd is 1.5V, i think i may be for portable applications (battery operated).
 

high impedance state

As far as my understanding go's, connecting PULL UP & PULL DOWN resistors will give the value which is designed for standby/floating mode.

If I was getting intermediate value(say 0.8v - NO LOGIC) & after connecting resistors if I had got 1.5v, then I could have drawn stronger conclusion on designed floating value.

But voltage values before & after connecting resistors is still the same 1.5v. Maybe I can conclude that designed standby value itself is 1.5v.

Thanks a bunch :)..
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top