XST warning tristates replaced by pull-up

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cmos babe

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pull-up yes

Hi I wanted to created a top-level block that contains two 8-bit tristate buffers ,one is connected to the input of a register and the other is connected to the output ...I got this warning :

WARNING:Xst:2042 - Unit zreg: 8 internal tristates are replaced by logic (pull-up yes): into1<0>, into1<1>, into1<2>, into1<3>, into1<4>, into1<5>, into1<6>, into1<7>.

into1(7:0) is the vector signal connecting the output of the first buffer to the input of the register..
 

internal tristates are replaced by logic

Looks like an optimization notification.

You don't need 3-state on the register inputs.
 

    C

    cmos babe

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tristates replaced by logic

You are right,I don't need one. I was looking at some design and trying to write code describing it blindly.

I wrote a behavioral describtion of a register with a tristate buffer connected to it at the output .

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity registerunit is
Port(clk,En,Eno: in std_logic;
	D: in std_logic_vector(7 downto 0);
		Q:out std_logic_vector(7 downto 0));
end registerunit;

architecture Behavioral of registerunit is	
signal G:std_logic_vector(7 downto 0);
begin

process(clk)

begin
if (clk'event and clk='1') then
	if En='1' THEN
	G<=D;
 	end if;
end if;
end process;
Process(G,eno)
begin
If Eno='0' THEN
Q<="ZZZZZZZZ";
else 
Q<=G;
end if;
	end process;
end Behavioral;
 

I'm getting a similar warning. This is just some code I wrote to figure out how I would code a bidirectional bus. I'm not sure why I'm getting the warning.

Code: 
library ieee;
use ieee.std_logic_1164.all;

entity test is
	port(clock: in std_logic);
end entity;

architecture structure of test is

component a
	port(clock: in std_logic;
		bbus: inout std_logic_vector(7 downto 0);
		cs: inout std_logic);
end component;


component b 
	port(clock: in std_logic;
		bbus: inout std_logic_vector(7 downto 0);
		cs: in std_logic);
end component;

signal bbus: std_logic_vector(7 downto 0);
signal cs: std_logic;

begin

	c1: a port map(clock, bbus, cs);
	c2: b port map(clock, bbus, cs);

end structure;
Code: 
library ieee;
use ieee.std_logic_1164.all;

entity b is
	port(clock: in std_logic;
		bbus: inout std_logic_vector(7 downto 0);
		cs: in std_logic);
end entity;

architecture behavior of b is
signal mem: std_logic_vector(7 downto 0);
signal state: integer range 0 to 1 := 0;
begin
	process(clock)
		begin
		if clock'event and clock = '1' then 
			case state is
				----------------- Read bus into mem
				when 0 =>
					if cs = '1' then
						mem <= bbus;
						state <= 1;
					else
						state <= 0;
					end if;
				----------------- Write to the bus
				when 1=>
					if cs = '0' then
						bbus <= mem;
						state <= 0;
					else
						bbus <= "ZZZZZZZZ";
						state <= 1;
					end if;
			end case;
		end if;
	end process;
end behavior;
Code: 
library ieee;
use ieee.std_logic_1164.all;

entity a is
	port(clock: in std_logic;
		bbus: inout std_logic_vector(7 downto 0);
		cs: inout std_logic);
end entity;

architecture behavior of a is
signal mem: std_logic_vector(7 downto 0) := "11110000";
signal state: integer range 0 to 1 := 0;
begin
	process(clock)
		begin
		if clock'event and clock = '1' then 
			case state is
				------------------ Write to the bus
				when 0 =>
				cs <= '1';
				if cs = '0' then
					bbus <= not mem;
				else
					bbus <= "ZZZZZZZZ";
				end if;
				state <= 1;
				------------------ Read from the bus
				when 1=>
				mem <= bbus;
				cs <= '0';			
			end case;
		end if;
	end process;
end behavior;
 

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