# XST synthesis error of an address sequence generator in Verilog

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#### samcheetah

i have made an address sequence generator in verilog. the following part gives the error

Code:
always @ (negedge init or negedge rst)
begin
if(rst==0)
begin
first = 14'b00_0000_0000_0000;
last = 14'b00_0000_0000_0000;
count = 13'b0_0000_0000_0000;
end
.
.
.
end

and i get the following error

Code:
ERROR:Xst:880 - seq.v line 47: Cannot mix blocking and non blocking assignments on signal <count>.
ERROR:Xst:880 - seq.v line 48: Cannot mix blocking and non blocking assignments on signal <addr>.
ERROR:Xst:899 - seq.v line 17: The logic for <first> does not match a known FF or Latch template.
ERROR:Xst:899 - seq.v line 18: The logic for <last> does not match a known FF or Latch template.
ERROR:Xst:899 - seq.v line 48: The logic for <addr> does not match a known FF or Latch template.
ERROR:Xst:899 - seq.v line 47: The logic for <count> does not match a known FF or Latch template.

#### echo47

xst 880

Need to see a full module, not just a code fragment.

Asynchronous reset can cause all sorts of problems.

#### samcheetah

xst 899

never mind. i dont know how i managed to write such stupid code that did nothing with the clock input. anyway its sorted and i have made the reset input synchronous with the clock.

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