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[SOLVED] Xst:737 Latches may be generated from incomplete case or if statements.

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arjun9989

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Hi,

I'm getting this warning again and again even though I've used all the states for my particular state machine.

what to do? see I've taken

reg[2:0] next_state,current_state;

parameter s0=0;
s1=1;
s2=2;
s3=3;
s4=4;
s5=6;
s6=7;

actually they were taken in binary form, so i mean to say that there is no other transition for a 3 bit signal. then, why should i bother about inferring a latch?

I'd appreciate if any one can help me?
 

qieda

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Hi,

you need to post your state machine, so that we can see if your code could generate latches.

regards
 

kornukhin

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Code:
reg[2:0] next_state,current_state;
 
parameter s0=0;
 s1=1;
 s2=2;
 s3=3;
 s4=4;
 s5=6;
 s6=7;
What about '=5'?
 

sakthikumaran87

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latch is found as u have not kept s7 state/defAULT STATE IN YOUR fsm.
 

arjun9989

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sorry,
I've not mentioned the 7th state.

these are my states

parameter idle=3'd0;
parameter non_sequential=3'd1;
parameter sequential=3'd2;
parameter busy=3'd3;
parameter single=3'd4;
parameter incr_def=3'd5;
parameter incr=3'd6;
parameter wait_state=3'd7;

and there is no other transition to generate a latch.
 

arjun9989

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module priority(clk,rst,req1,req2,req3,req4,pri_1,pri_2,pri_3,pri_4,gr1,gr2,gr3,gr4,pri_change);

input clk,rst,req1,req2,req3,req4,pri_change;

input [1:0]pri_1,pri_2,pri_3,pri_4;

output reg gr1,gr2,gr3,gr4;
reg [3:0] req_set3,req_set2,req_set1,req_set0;
reg [3:0]stat=4'b0000;
reg [3:0] current_state,next_state;
wire csr0,csr1,csr2,csr3,csr4;
wire reg0,reg1,reg2,reg3,prior_0,prior_1,
prior_2,prior_3,prior3_0,prior3_1,prior3_2,
prior3_3,prior0_0,prior0_1,prior0_2,prior0_3,
prior1_0,prior1_1,prior1_2,prior1_3,prior2_0,
prior2_1,prior2_2,prior2_3,req_1,req_2,req_3,
req_4;

parameter idle=4'b0000;
parameter s0=4'b0001;
parameter s1=4'b0010;
parameter s2=4'b0011;
parameter s3=4'b0100;
parameter s4=4'b0101;
parameter grant1=4'b0110;
parameter grant2=4'b0111;
parameter grant3=4'b1000;
parameter grant4=4'b1001;

parameter priority_0=2'b00;
parameter priority_1=2'b01;
parameter priority_2=2'b10;
parameter priority_3=2'b11;

always @(posedge clk or negedge rst)
begin
if(!rst)
begin
current_state<=idle;
end
else
begin
current_state<=next_state;
end
end


assign prior3_0=(req1&!(pri_1^priority_3));
assign prior3_1=(req2&!(pri_2^priority_3));
assign prior3_2=(req3&!(pri_3^priority_3));
assign prior3_3=(req4&!(pri_4^priority_3));

assign prior0_0=(req1&!(pri_1^priority_0));
assign prior0_1=(req2&!(pri_2^priority_0));
assign prior0_2=(req3&!(pri_3^priority_0));
assign prior0_3=(req4&!(pri_4^priority_0));

assign prior1_0=(req1&!(pri_1^priority_1));
assign prior1_1=(req2&!(pri_2^priority_1));
assign prior1_2=(req3&!(pri_3^priority_1));
assign prior1_3=(req4&!(pri_4^priority_1));

assign prior2_0=(req1&!(pri_1^priority_2));
assign prior2_1=(req2&!(pri_2^priority_2));
assign prior2_2=(req3&!(pri_3^priority_2));
assign prior2_3=(req4&!(pri_4^priority_2));

assign prior_0=(prior0_0)||(prior0_1)||(prior0_2)||(prior0_3);
assign prior_1=(prior1_0)||(prior1_1)||(prior1_2)||(prior1_3);
assign prior_2=(prior2_0)||(prior2_1)||(prior2_2)||(prior2_3);
assign prior_3=(prior3_0)||(prior3_1)||(prior3_2)||(prior3_3);

assign csr0=(~stat[3]&~stat[2]&~stat[1]&~stat[0]);
assign csr1=(~stat[3]&~stat[2]&~stat[1]&stat[0]);
assign csr2=(~stat[3]&~stat[2]&stat[1]&~stat[0]);
assign csr3=(~stat[3]&stat[2]&~stat[1]&~stat[0]);
assign csr4=(stat[3]&~stat[2]&~stat[1]&~stat[0]);

always @(*)
begin

case(current_state)

idle: begin
if(prior_3)
next_state=s3;
else if(prior_2&&!prior_3)
next_state=s2;
else if(prior_1&&!prior_2&&!prior_3)
next_state=s1;
else if(prior_0&&!prior_1&&!prior_2&&!prior_3)
next_state=s0;
else
begin
next_state=idle;
end
end

s0: begin
req_set0={prior0_3,prior0_2,prior0_1,prior0_0};
if(req_1)
next_state=grant1;
else if(req_2)
next_state=grant2;
else if(req_3)
next_state=grant3;
else if(req_4)
next_state=grant4;
else
next_state=idle;
end

s1: begin
req_set1={prior1_3,prior1_2,prior1_1,prior1_0};
if(req_1)
next_state=grant1;
else if(req_2)
next_state=grant2;
else if(req_3)
next_state=grant3;
else if(req_4)
next_state=grant4;
else
next_state=idle;
end
s2: begin
req_set2={prior2_3,prior2_2,prior2_1,prior2_0};
if(req_1)
next_state=grant1;
else if(req_2)
next_state=grant2;
else if(req_3)
next_state=grant3;
else if(req_4)
next_state=grant4;
else
next_state=idle;
end
s3: begin
req_set3={prior3_3,prior3_2,prior3_1,prior3_0};
if(req_1)
next_state=grant1;
else if(req_2)
next_state=grant2;
else if(req_3)
next_state=grant3;
else if(req_4)
next_state=grant4;
else
next_state=idle;
end

grant1: begin

stat=4'b0001;

if(req1==1'd0||pri_change)
begin
next_state=idle;
end
end

grant2: begin

stat=4'b0010;

if(req2==1'd0||pri_change)
begin
next_state=idle;
end
end

grant3: begin

stat=4'b0100;

if(req3==1'd0||pri_change)
begin
next_state=idle;

end
end

grant4: begin
stat=4'b1000;

if(req4==1'd0||pri_change)
begin
next_state=idle;
end
end

default: begin
next_state=4'bxxxx;
stat=4'bxxxx;
req_set0=4'bxxxx;
req_set1=4'bxxxx;
req_set2=4'bxxxx;
req_set3=4'bxxxx;
end
endcase
end

always @(posedge clk or negedge rst)
if(!rst)
begin
gr1<=1'd0;
gr2<=1'd0;
gr3<=1'd0;
gr4<=1'd0;
end
else
begin
gr1<=1'd0;
gr2<=1'd0;
gr3<=1'd0;
gr4<=1'd0;
case (next_state)
idle,s0,s1,s2,s3:begin
gr1<=1'd0;
gr2<=1'd0;
gr3<=1'd0;
gr4<=1'd0;
end
grant1:gr1<=1'd1;
grant2:gr2<=1'd1;
grant3:gr3<=1'd1;
grant4:gr4<=1'd1;
endcase
end



assign reg0=(req_set0[0]||req_set1[0]||req_set2[0]||req_set3[0]);
assign reg1=(req_set0[1]||req_set1[1]||req_set2[1]||req_set3[1]);
assign reg2=(req_set0[2]||req_set1[2]||req_set2[2]||req_set3[2]);
assign reg3=(req_set0[3]||req_set1[3]||req_set2[3]||req_set3[3]);

assign req_1=(csr0&&reg0) || (csr4&&reg0) || (csr1&&reg0&&!reg1&&!reg2&&!reg3)|| (csr3&&!reg3&&reg0) || (csr2&&req1&&!req3&&!req4);
assign req_2=(csr0&&reg1) || (csr1&&reg1) || (csr2&&reg1&&!reg0&&!reg2&&!reg3)|| (csr4&&!reg0&&reg1) || (csr3&&reg1&&!reg3&&!reg0);
assign req_3=(csr0&&reg2) || (csr2&&reg2) || (csr3&&reg2&&!reg0&&!reg1&&!reg3)|| (csr1&&!reg1&&reg2) || (csr4&&reg2&&!reg0&&!reg1);
assign req_4=(csr0&&reg3) || (csr3&&reg3) || (csr4&&reg3&&!reg0&&!reg1&&!reg2)|| (csr2&&!reg2&&reg3) || (csr1&&reg3&&!reg1&&!reg2);

endmodule

Hi all, this is the code where i'm getting these are warnings:

WARNING:Xst:737 - Found 4-bit latch for signal <next_state>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <req_set0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <req_set1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <req_set2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <req_set3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <stat>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
 

qieda

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Hi

critical for latches are combinatorical blocks.
when I look into your always @(*) block with the big case the states

grantX will generate latches.

e.g look into grant4

grant4: begin
stat=4'b1000;

if(req4==1'd0||pri_change)
begin
next_state=idle;
end
end

when req4==1'd1 and pri_change the next_state is not defined -> this will generate an latch

an easy way to solve this is to give next_state a default assignment at the beginning of your combinatorical block.

e.g. in this way

....
always @(*)
begin

next_state = current_state;

case(current_state)
....

regards

- - - Updated - - -

In addition, I think your default state can not be synthesised.
when you look in your warnings, you see also that the signal stat and req_setX is not used in all case conditons so this will generate latches


best regards
 

sakthikumaran87

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default: begin
next_state=4'bxxxx;
stat=4'bxxxx;
req_set0=4'bxxxx;
req_set1=4'bxxxx;
req_set2=4'bxxxx;
req_set3=4'bxxxx;
end
endcase
end

Not a good coding practise. Never assign to 'x'.
 

arjun9989

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Thank you Qieda,

I found the reason from your suggestion and there are no warnings. My code is fully synthesized.
 

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