#### dinesh106

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Plz correct my error..

Giv me the idea for this r correct the error and send to my mail id : 54321.dinesh@gmail.com

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Error in Xilinx:

Xst:528 - Multi-source in Unit <twomux> on signal <cout>

Program in VHDL:

TWOMUX:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity twomux is port

(a,b:in std_logic_vector(1 downto 0);

cin:in std_logic;

kut std_logic_vector(1 downto 0);

coutut std_logic);

end twomux;

architecture struct of twomux is

component twobitadd is port

(a,b:in std_logic_vector(1 downto 0);

cin:in std_logic;

sut std_logic_vector(1 downto 0);

coutut std_logic);

end component;

component twobitadd0 is port

(a,b:in std_logic_vector(1 downto 0);

cin:in std_logic;

sut std_logic_vector(1 downto 0);

coutut std_logic);

end component;

component muxtwo is

port(m: in std_logic_vector(1 downto 0);

n: in std_logic_vector(1 downto 0);

o: in std_logic;

cout : out std_logic_vector(1 downto 0));

end component;

signal s1,s2:std_logic_vector(1 downto 0);

begin

a1:twobitadd0 port map(a,b,'0',s1,cout);

a2:twobitadd port map(a,b,'1',s2,cout);

a3:muxtwo port map(s1,s2,cin,k);

end struct;

Sub Programs:

2bitadd0:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity twobitadd0 is port

(a,b:in std_logic_vector(1 downto 0);

cin:in std_logic;

sut std_logic_vector(1 downto 0);

coutut std_logic);

end twobitadd0;

architecture struct of twobitadd0 is

component fulladder is port

(a,b,c:in std_logic;

s,c1ut std_logic);

end component;

signal c1:std_logic;

begin

a1:fulladder port map(a(0),b(0),cin,s(0),c1);

a2:fulladder port map(a(1),b(1),c1,s(1),cout);

end struct;

2bitadd:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity twobitadd is port

(a,b:in std_logic_vector(1 downto 0);

cin:in std_logic;

sut std_logic_vector(1 downto 0);

coutut std_logic);

end twobitadd;

architecture struct of twobitadd is

component fulladder is port

(a,b,c:in std_logic;

s,c1ut std_logic);

end component;

signal c1:std_logic;

begin

a1:fulladder port map(a(0),b(0),cin,s(0),c1);

a2:fulladder port map(a(1),b(1),c1,s(1),cout);

end struct;

Mux(2:1):

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

entity muxtwo is

port(m: in std_logic_vector(1 downto 0);

n: in std_logic_vector(1 downto 0);

o: in std_logic;

cout : out std_logic_vector(1 downto 0));

end muxtwo;

architecture mu of muxtwo is

begin

process(m,n,o)

begin

if o ='0' then cout<=m;

else

cout<=n;

end if;

end process;

end mu;