Xst:1290 Hierarchical error in verilog

[heipo]

Xst:1290 Hierarchical error in verilog on Xilinix

Hi. I have been getteing this type of error in verilog and cannot figure out the issue: "WARNING:Xst:1290 - Hierarchical block <inst_debo1> is unconnected in block <MainModule>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <inst_debo2> is unconnected in block <MainModule>.
It will be removed from the design."

Any help, hint would be appreciated, thanks.

Here is the top most module:

module MainModule(inclk, butt1, butt2, butrst, muxout, loc);

input inclk;
input butt1;
input butt2;
input butrst;

output wire [7:0] muxout;
output wire [3:0] loc;

wire dout1, dout2;
wire [3:0] incinput1, incinput2;
wire [7:0] output1, output2;
wire [1:0] select;

debouncer inst_debo1(
.inclock(inclk),
.rst(butrst),
.butt(butt1),
.dout(dout1)
);

debouncer inst_debo2(
.inclock(inclk),
.rst(butrst),
.butt(butt2),
.dout(dout2)
);

numinc inst_numinc(
.sel1(dout1),
.sel2(dout2),
.out1(incinput1),
.out2(incinput2)
);

Here is the debouncer:

module debouncer(inclock, rst, butt, dout);


input inclock;
input rst;
input butt;

output dout;
reg state;
reg dout;
reg count;

initial begin
count=0;
state=2'b00;
end

always @(posedge inclock) begin


if (rst) begin
state <=2'b00; end
else begin
case(state)
2'b00:
begin
if (butt==1)
begin
state <= 2'b01;
end
else
begin
state <= 2'b00;
end
end

2'b01:
begin
if ( (butt==1)&&(count>=49) )
begin
state <= 2'b10;
end
else
begin
state <= 2'b00;
count=count+1;
end
end

2'b10:
begin
if (butt==1)
begin
state <= 2'b10;
end
else
begin
state <= 2'b11;
end
end

2'b11:
begin
if (butt==1)
begin
state <= 2'b11;
end
else
begin
state <= 2'b00;
end
end

endcase
end

if (state==2'b00) begin
dout<=0; end
else if (state==2'b01) begin
dout<=0; end
else if (state==2'b10) begin
dout<=1; end
else if (state==2'b11) begin
dout<=0; end


end

 

[mrflibble]

The warning says it all really...

WARNING:Xst:1290 - Hierarchical block <inst_debo1> is unconnected in block <MainModule>. It will be removed from the design.

Your top level module "MainModule" instantiates a debouncer named "inst_debo1". And you did not make any logical connections to the outputs of that inst_debo1. And XST will optimize away anything that has nothing connected to the outputs. Same story for inst_debo2.

Looking at your code, it looks like you have connected the dout1 + dout2 correctly as the outputs. However, if THOSE in turn are not used for anything then the whole thing is still going to be optimized away.

Now dout1 and dout2 look to be inputs to inst_numinc. Since you didn't include the code for that, not sure ... But the main theme here is, if you don't use the output for something (output has no load), then it will be optimized away.

 

[heipo]

Thanks.

Now dout1 and dout2 look to be inputs to inst_numinc. Since you didn't include the code for that, not sure

I am using the outputs from the debouncer only as variables in conditional statements in the numinc function. Do you think that may have caused the error?

 

[mrflibble]

Without all of the code, no way to be sure. But that warning has everything to do with it being optimized away due to having no load. So either change your design so that you are sure there is a load for those signals, or have a look at the KEEP and SAVE flags.