xilinx multicycle paths
For your example: suppose you have a 10 ns clock period and a multiplier that takes 13 ns to calculate the answer.
If you make your control path that it launches the multiplication at clock edge @ time = 0 ns.
If you don't clock (clock enable=false) what's coming out of the multiplier at time = 10ns, and clock the result in at time = 20 ns, you have created a "multicycle path". The path itself seems 10 ns (because it is between 2 flipflops that are attached to a 10 ns clock period. But as you (human) know (by design) that one of the clocks is never enabled one in 2 clock edges, and the effective data flow only is 20 ns, this is a fake constraint. So you have to relax it by telling the Xilinx optimisation tools that they only need to take 20 ns as constraint if going THRU the multiplier.
Hope this was helpful. Look in the Xilinx Answers Database for training on this and other constraints.