Xilinx's Video timing controller IP

[honnaraj.t]

Hi,
I am using Xilinx's "video timing controller ip" for my image processing pipeline/design. I have downloaded hardware evaluation license for the ip. I have implemented this along with other ip's.

I am facing following issue

1) I am feeding input to this ip, but it's out is always 0.
2) To check whether this ip is alive, I tried to access 0x10 register of the ip.(Note: this register is read only memory having version number). But it is returning 0x0000 value.

Looking for:
1) kindly let me know is any implementation issue with ip for hardware evaluation license.
2) Any special setting I should do, apart from normal ip implementation.
3) Kindly share supporting material like example design, design steps etc.


Thank you in advance.

Rgds
Honnaraju.T

 

[kaiserschmarren87]

Do yu have the simulation output ? Simulation result will help to understand.
Have yu cross checked the IP configuration manual ? If you could post those details will help to analyse even for others.
According to LogiCore IP Video Timing Controller v2.1:

The Full System Hardware Evaluation license is available at no cost and lets you fully integrate the core into an FPGA design, place-and-route the design, evaluate timing, and perform functional simulation
of the Video Timing Controller core.