verilog rs232 code
Jayson,
If you have access to Xilinx ISE, the "Hello World" example using the
XAPP223 can be put together using four files:
- the two .EDN files included in XAPP223;
- one VHDL file with all of your code;
- one .UCF file containing pin designations and your clock rate.
The .UCF can have only 5 lines:
NET "CLKIN" TNM_NET = "CLKIN";
TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 80 ns HIGH 50 %;
NET "CLKIN" LOC = "P88";
NET "SERIAL_TXD" LOC = "P83";
NET "SERIAL_RXD" LOC = "P60";
where CLKIN is the input clock, in this case 12.5 MHz, SERIAL_TXD
and SERIAL_RXD are the serial output and input and the PXX are
the pin locations on your development board.
The VHDL code must contain a clock buffer, which is basic
infrastructure. I strongly suggest you read at least one of these
documents, that explain basic clock treatment:
Using the Virtex Delay-Locked Loop **broken link removed**
Using Delay-Locked Loops in Spartan-II FPGAs **broken link removed**
Specifically for XAPP223, you need to supply a signal called
EN_16_X_BAUD, which is described in the documentation. All you
have to do then, if I am not mistaken, is connect signals directly.
Does this help?