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Xilinx XAPP223: RS-232 Flow Control

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dingo

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rs232 flow control

I am trying to use the free reference design from Xilinx:

XAPP223 200MHz UART with Internal 16-Byte Buffer
http://www.xilinx.com/ipcenter/cata...e_xapp223_200mhz_uart_with_16_byte_buffer.htm

I am having a hard time using it since it does not have the flow control
implemented, as when using RTS and CTS signals. How do you implement
these RTS and CTS signals? Does anyone have an easy solution for this?
 

Aircraft Maniac

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xilinx rs232

Why dont u try checking out the RS-232 core on

www.opencores.org

maybe its documentation and code will be of some help.

Aircraft Maniac
 

Jayson

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xapp223

How do you use the core? I have a dev board, but how do do something simple like send a"Hello World"

My question should really be: how do I use cores in my design, where do I implement them? If this was C programming it would be easy just one #include <somecore.h> but how about in VHDL? and then how do I integrate that into my design?


- Jayson
 

dingo

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rs232 verilog code

Aircraft Maniac,
Thanks for your tip. I haven't been able to access OpenCores since
(at least) yesterday, looks as if they are down. I always avoid
OpenCores because people there tend to use Verilog, and I use VHDL.
I will wait until it is up.

Jayson,
Hmmm... The component instantiation is quite simple in VHDL. It is
shown on page 2 and 3 of the documentation. It's quite straight forward.
Are you acquainted with VHDL ?



I have to reformulate my initial question. After extensive testing using
several debugging methods, I got to the conclusion that I do not have
a flow control (handshaking) problem. The data that comes out of the
RX module is always garbled. In one VGA video screen (300 kBytes)
I get something between 2 and 20 errors, which multipy themselves
since the RX's state machine appears to loose sync, generating long
bursts of garbage. I do not know what is causing this problem. I have
tried reducing the baud rate, but this has no effect. When the machine
receives a character zero (represented as "0000000001", whre the
first '0' is the start bit and the last '1' is the stop bit) it gets back into
sync. I am not sure if zero is the only character with this property.
 

Jayson

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xilinx rs232 vhdl

not entirely acquainted with VHDL, what I want to do is just plug it in and see it go.

- Jayson
 

dingo

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rs232 xilinx

I found this on OpenCores:

Project: Serial Uart http://www.opencores.org/projects/miniuart2/
which is written in VHDL, but has two problems:
- no FIFO;
- no flow control.

There are other two projects written in Verilog, one is a complete 16550,
which seems to be kind of huge:
Project: UART 16550 core http://www.opencores.org/projects/uart16550/

and another one which seems absolutely perfect (except for the Verilog)
Project: Simple Asynchronous Serial Controller http://www.opencores.org/projects/sasc/
and uses "102 LUTs" (did the author mean CLBs?) against the 15 CLBs
that the XAPP223 uses (no flow control and does not work right for me).

Conclusion: there is no win-win situation on OpenCores for someone
that uses VHDL and needs a simple RS-232 interface.



Does anyone know of some Verilog to VHDL translator ?
 

dingo

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verilog rs232 code

Jayson,

If you have access to Xilinx ISE, the "Hello World" example using the
XAPP223 can be put together using four files:

- the two .EDN files included in XAPP223;
- one VHDL file with all of your code;
- one .UCF file containing pin designations and your clock rate.

The .UCF can have only 5 lines:

NET "CLKIN" TNM_NET = "CLKIN";
TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 80 ns HIGH 50 %;
NET "CLKIN" LOC = "P88";
NET "SERIAL_TXD" LOC = "P83";
NET "SERIAL_RXD" LOC = "P60";

where CLKIN is the input clock, in this case 12.5 MHz, SERIAL_TXD
and SERIAL_RXD are the serial output and input and the PXX are
the pin locations on your development board.

The VHDL code must contain a clock buffer, which is basic
infrastructure. I strongly suggest you read at least one of these
documents, that explain basic clock treatment:

Using the Virtex Delay-Locked Loop http://www.xilinx.com/xapp/xapp132.pdf
Using Delay-Locked Loops in Spartan-II FPGAs http://www.xilinx.com/xapp/xapp174.pdf

Specifically for XAPP223, you need to supply a signal called
EN_16_X_BAUD, which is described in the documentation. All you
have to do then, if I am not mistaken, is connect signals directly.

Does this help?
 

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