I am trying to understand SPI protocols. So i tried to model a SPI master device. But whien i synthesize i get warnings like
1. Xst:1306 - Output <rcx_buffer> is never assigned.
2. Xst:646 - Signal <rcx_buff<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
my code is:
Code Verilog - [expand] |
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| send_buff[0]=trans_buff[7]; //copy msb of trans_buff in send_buff
mosi=send_buff[7]; //send msb first
send_buff=send_buff<<1; // left shift for next bit to send
trans_buff=trans_buff<<1;
end |