xilinx warnings XST 1306 and XST 646

[bitu_tzp]

I am trying to understand SPI protocols. So i tried to model a SPI master device. But whien i synthesize i get warnings like
1. Xst:1306 - Output <rcx_buffer> is never assigned.
2. Xst:646 - Signal <rcx_buff<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

my code is:

---

Code Verilog - [expand]
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module master(inp,pin,rst,miso,sck,mosi,trans_buff,send_buff,rcx_buffer);
input sck,rst,miso,pin;
input [7:0] inp;
output mosi;
output [7:0] trans_buff,send_buff;
output [7:0] rcx_buffer;
 
reg mosi;
reg [7:0] trans_buff;      // buffer for storing the byte to send
reg [7:0] send_buff;      // buffer for the byte to be send
reg [7:0] rcx_buff=8'b00000000;     // buffer for storing the byte received
 
 
always @(posedge sck)
begin   
    if(rst)
    begin
        trans_buff=8'b00000000;
        send_buff=8'b00000000;
    end
    else 
        begin
    if(pin)
        trans_buff=inp;      //capturing the input
    else
    begin
        send_buff[0]=trans_buff[7];     //copy msb of trans_buff in send_buff
        mosi=send_buff[7];              //send msb first
        send_buff=send_buff<<1;    // left shift for next bit to send
        trans_buff=trans_buff<<1;
    end
       end
end
 
always @(negedge sck)
begin
    rcx_buff[0]=miso;         //capture serial input in negedge of sck
    rcx_buff=rcx_buff<<1;
end
endmodul

---

 

[FvM]

If you check where output rcx_buffer is assigned in your code, you don't find any place. May be you confused rcx_buffer and rcx_buff?

Generally, it's bad coding style to use blocking assigments in sequential always blocks. Suggest to rewrite the code with non-blocking assignments and then start to fix the errors.

 

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I am trying to understand SPI protocols. So i tried to model a SPI master device. But whien i synthesize i get warnings like
1. Xst:1306 - Output <rcx_buffer> is never assigned.
2. Xst:646 - Signal <rcx_buff<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

my code is:

---

Code Verilog - [expand]
1
2
3
4
5
send_buff[0]=trans_buff[7];     //copy msb of trans_buff in send_buff
        mosi=send_buff[7];              //send msb first
        send_buff=send_buff<<1;    // left shift for next bit to send
        trans_buff=trans_buff<<1;
    end

---

I'm pretty certain this code will behave differently after synthesis than it does in simulation due to the use of blocking statements. You are treatiing this sequence like a progaramming task in C. Verilog is a hardware description language. If you want the correct flip-flop behavior assign each bit of the flip-flops with a single statement instead of multiple sequences of statements.