Xilinx VP2p : Read Back and Active Partial Reconfiguration

[Mirzaaur]

Dear all,

Active partial reconfiguration and read back of configuration for Virtex II pro doesnt work if the design has used any of the shift register LUT from xilinx:-

I am trying to find a way where I can set a constraint in UCF file so the mapper never use these components by :-

CONFIG PROHIBIT = SRL16;
CONFIG PROHIBIT = SRL16_1 ;
CONFIG PROHIBIT = SRL16E;
CONFIG PROHIBIT = SRL16E_1 ;
CONFIG PROHIBIT = SRLC16;
CONFIG PROHIBIT = SRLC16_1;
CONFIG PROHIBIT = SRLC16E;
CONFIG PROHIBIT = SRLC16E_1;

BUT! SRL_16 is not a site, its component...

how to prohibit the xilinx mapper from using and of the above stated compnent so the active read back doesnt get in troubles?:?:?

any hint / clue?:?:

cheers,

mirzaaur

 

[bigdogguru]

I do not have any experience dealing with your particular problem.

However, I just start reading an excellent book on the subject of reconfigurable computing:

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

The text is one of the best and only books on the subject. I've found it to be packed full of good references and real world examples.

If you do not already have a copy, you may want to pick one up.