Xilinx Virtex4: Connecting a PowerPC module with userlogic

[rfsweden]

I'm using a Xilinx ML403, Virtex4 board.

I have:

PowerPC system that works fine alone.

+

Userlogic that works fine alone.

My problems is that I need to run both these modules in parallel, at the same chip.

I have tried to simply instansiate the Userlogic in my "system_stub.vhd" file

If you are familiar to EDK and ISE you should know what I'm talking about.

Anyways, I have to share the sys_clk_pin_IBUFG between the userlogic
and the PowerPC system and this is the cause of the problem.

Because when I do this, the userlogic runs fine, but the PowerPC system don't

Any ideas why this happens?
My thought is that I cannot instansiate the userlogic in the system_stub.vhd
Maby this file needs to be "clean"

But how could I instansiate it otherwise?

 

[eziggurat]

Re: Xilinx Virtex4: Connecting a PowerPC module with userlog

I am assume you instantiate a BRAM in the wizard to store the PowerPC code and the user logic is part of the EDK project. When generated the netlist, you need to select it as a sub-module and this will generatea system.vhd. You need to create a top_level to incorporate the generated module. Also use the MHS file to route the clock to the correct modules.

 

[BuBEE]

do you have a turorial for powerpc ?

 

[zcq]

There is EDK tutorial in XILINX'S web.

zcq