I agree with all said.
However, I'm dealing here with a given design.
The application logic writes to the whole address space of the memory controller and then reads back the data.
The design fails to meet the required bandwidth and I think it happens because of inefficienties in the part of the user code that manages the DDR controller.
However, to prove it's not the DDR controller's fault, I've been asked to measure it's bandwidth (without any changes to the application's logic).
All I need is an "I'm not idle" signal from the DDR controller (this signal will be asserted when the controller is busy moving data + doing all the house keeping associated with it...).