Old Nick
Advanced Member level 1
Hi,
I'm working on designing an acquisition system which utilises a Spartan 3 FPGA. The input data is clocked with differential clocks (lvds datra), I am having a bit of trouble with timing constraints, meeting them and knowing if I'm specifying them correctly.
Using the timing constraints editor I have specified a clock (RxCLK) with a frequency of 240 MHz, and then tried to generate a reciprocal clock(RxCLKNot) by referencing a clock to the RxCLK with a positive phase shift os 2.08333ns.
I have also tried to generate tboth clocks independently in thge constraints editor just swapping the 'Initial clock edge' from high to low.
I get better timing closure doing the latter, but I have little confidence in it. In fact I have little confidence in either method. I am not sure if I have over constrained the clocks etc.
Does anyone know the correct way to do this, or have any advice in acheiving timing closure etc.
Cheers,
Nick
I'm working on designing an acquisition system which utilises a Spartan 3 FPGA. The input data is clocked with differential clocks (lvds datra), I am having a bit of trouble with timing constraints, meeting them and knowing if I'm specifying them correctly.
Using the timing constraints editor I have specified a clock (RxCLK) with a frequency of 240 MHz, and then tried to generate a reciprocal clock(RxCLKNot) by referencing a clock to the RxCLK with a positive phase shift os 2.08333ns.
I have also tried to generate tboth clocks independently in thge constraints editor just swapping the 'Initial clock edge' from high to low.
I get better timing closure doing the latter, but I have little confidence in it. In fact I have little confidence in either method. I am not sure if I have over constrained the clocks etc.
Does anyone know the correct way to do this, or have any advice in acheiving timing closure etc.
Cheers,
Nick