Xilinx timing constraint differential clock

[Old Nick]

Hi,
I'm working on designing an acquisition system which utilises a Spartan 3 FPGA. The input data is clocked with differential clocks (lvds datra), I am having a bit of trouble with timing constraints, meeting them and knowing if I'm specifying them correctly.
Using the timing constraints editor I have specified a clock (RxCLK) with a frequency of 240 MHz, and then tried to generate a reciprocal clock(RxCLKNot) by referencing a clock to the RxCLK with a positive phase shift os 2.08333ns.
I have also tried to generate tboth clocks independently in thge constraints editor just swapping the 'Initial clock edge' from high to low.
I get better timing closure doing the latter, but I have little confidence in it. In fact I have little confidence in either method. I am not sure if I have over constrained the clocks etc.
Does anyone know the correct way to do this, or have any advice in acheiving timing closure etc.

Cheers,

Nick

 

[permute]

Translate/MAP only needs to have a TNM_NET and TIMESPEC constraint on the _P input pad. The use of TNM_NET will push though the ibufgds/ibufds.

Keep in mind that the external interface might need offset constraints, or the clock might need to go to a DCM in zero-delay buffer mode for the clocking of the data into the FPGA.

There are reports about what timing constraints were used. You can also make a verbose post-par timing report (.twr) that contains the worst paths from each constraint. This will at least show you some analyzed paths.