xilinx timing analyzer

[nikhilindia85]

can any one explain how to do timing analysys in xilinx.my design is having timing violations.its urgent.

 

[echo47]

It's a problem-solving task that varies from project to project. For some general guidelines, try the "Design Considerations" chapter in the ISE "Synthesis and Simulation Design Guide". Also read the "TRACE" chapter in the ISE "Development System Reference Guide". TRACE helps you pinpoint the timing problems.

If your design is failing timing by a small amount, try increasing the MAP and PAR effort settings, or enable timing-driving mapping. That usually improves the timing somewhat, but not dramatically.

 

[vlsi_freak]

Hi.

Check your timing report first.

Now see the paths which does not meet timing. If possible try to register those input. Registering signals will have good impact on your timing. Also see that register retiming option is enabled in your synthesizer.

Sometimes, timing reports give negative slack timing in the I/O areas. You can neglect violations in FPGA IO Buffers.

Hope it helps.

Thanks