Xilinx synthesize error generation

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sherif123

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Sometimes I synthesize a big design using RTL and some already synthesized ngc files. If I forgot to add some correct vhd file to the .prj file, the synthesize tool continues its work and assumes that it 's a black box. But in the mapping stage, an error is generated. I need to know if there is an available synthesize option to force the synthesize tool to generate an error early??
Thanks
 

If you use direct instantiation and not components, it checks the entity rather than the component, and will throw and error at the elaboration stage.
You should never need to use components unless you instatiate verilog from your VHDL, or some library uses them.
 
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