I am using Xilinx Vivado 2018.3.
I tried to use the synthesis directives 'synthesis translate_off/on' within a VHDL 2008 package definition.
The xsim compiler gave me errors for that. Are the directives not supported at that place?
I have consulted UG901, Chapter2, and there it is only mentioned that "This attribute can only be set in the RTL." In my opinion the package definition part is also a valid RTL region.
Or is this problem Xilinx specific?
Any info on how other synth tools behave when these directives are used within a VHDL 2008 package definition?
Well in my design. IT works for synthesis. However I didn't use xsim for simulation because it couldn't handle vhdl2008.
Examples of
if rst then
killed the xsim. It just cannot handle inferred (??) operator. Therefore I'm not surprised if it cannot handle pragma commands. Give RTL_SYNTHESIS OFF a go, if that fails then you're in a situation where Xilinx can handle it for synthesis but not simulation.