Xilinx Startup_virtex4

[ukapil]

startup_virtex4

Hi,
When i use STARTUP_VIRTEX4 block in my design & do synthesis & PAR & then use the post PAR netlist for simulation, do i have to include glbl.v for simulation ?

 

[Big Boy]

x_ramb16

No, this is done automatically. However, I did got some issue with ISE 7.1, with STARTUP_SPARTAN3.

When simulating post P&R, the generated source file was missing GTS declaration. It only contained GSR, which was took from reset signal, but GTS was tied low in my design. However, the generated file did not assign anything to the UUT GTS wire. The simulation thus end-up having all outputs tri-stated (which obviusly doesn't match reality).

I had to write, in the testbench file:

assign uut.GTS = glbl.GTS; //Note that 'uut' is simply the name of the unit-under-test module instance declared in the testbench.

Or you could simply assign 0 to uut.GTS.

 

[ukapil]

I am also having some problem with 7.1. With 6.3 SP3 it works fine.

 

[srik_naidu]

hi,
just now i was started using xilinx 7.1i. i got some problems.

with regards,
srik.

 

[no_mad]

Hi all,

I hope all of you can give details of your probs so that for those whose going to start using ISE7.1 can be aware of these issues.

Please share your probs.

Thanx in advance

 

[Sparc]

Hi,
I am using ISE7.1 with all the updates available. I got some problem earlier with "glbl.v" but was solved when i later recompiled it and included explicitly with vsim.

Now, i hv a different problem i am trying post-synthesis simulation with BlockRAMs targetted on Virtex4, post-synthesis model is compiled but after implementation while compiling post-translation model, it gives following error:

# ** Error: macc5x100_par_translate.vhd(2292): Unknown identifier 'en_ecc_read'.
# ** Error: macc5x100_par_translate.vhd(2293): Unknown identifier 'en_ecc_write'.

I searched a bit for that and find that ecc probably means error correction code and en_ecc_read/write are generic ports in 'x_Ramb16' component defined in 'simprim_VITAL_mti.vhd' and is only in updated version. I hv recompiled all the device libraries but problem still persists.
If you guys can throw out some ideas regarding this.
I am using ModelSim6.0 version.

Thanks always

 

[ukapil]

I confirmed from Xilinx. it is a bug in 7.1. But they say it should work on board !

 

[Sparc]

# ** Error: macc5x100_par_translate.vhd(2292): Unknown identifier 'en_ecc_read'.
# ** Error: macc5x100_par_translate.vhd(2293): Unknown identifier 'en_ecc_write'.

This of my problem has been solved. I closed my all present simulations and recompiled simprim library. And this time i didn't face any problems in compiling Post-Xlate model.
Thanx..