buenos
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Hi
I recently found on the Xilinx website taht the Spartan-6 PCI-express endpoint has two datasheets (a year ago there was one) one original and one with AXI4 bus interconnect option.
How do they distinguish? Is it that the new silicon revision is equipped with the AXI4 interface on the hard IPs, or something to do with new version of CoreGenerator (making wrappers with the new interface)?
I recently found on the Xilinx website taht the Spartan-6 PCI-express endpoint has two datasheets (a year ago there was one) one original and one with AXI4 bus interconnect option.
How do they distinguish? Is it that the new silicon revision is equipped with the AXI4 interface on the hard IPs, or something to do with new version of CoreGenerator (making wrappers with the new interface)?