Xilinx spartan 3an memory regarding

[Lokesh Waran]

Dear all,

Presently we are doing some automation operation using micro controllers but i wish to change the technology to CPLD/FPGA .So, i wrote some verilog program in XILINX (XC9572XL) but it has 2 micro-cells of memory so i could not able implement the all coding in to that device . So, i tried to go for FPGA spartan 3AN (XC3S50AN) device. But I have confused with logic cells in spartan 3an and macrocells in CPLD memory like how much line of coding can able to write in spartan 3an device the sparatan XC3S50AN has 1584 logic cells specified in a data sheet. But I need the following memory specifications for my process.

TECHNICAL SPECIFICATIONS TO BE NEED

4K Flash Memory
16K RAM
UART-1number
Timer 16Bit- 2numbers
External Interrupts-3Numbers
Internal Core Frequency -100 Mhz
Minimum I/O - 60 above Pins
Package type -TQFP/QFN

Xilinx JTAG Platform cable (DS-10) Compatibility

thanks for all ..............

 

[ads-ee]

Seems to me that you should be able to fit what you require into the XC3S200AN. That part has 4Mb flash bits but only needs 1168Kb of flash for configuration. Read UG333 to learn how to access the flash after configuration.

Read the Spartan 3AN datasheet DS557 to see that the part you planned on using has only 54Kb of block RAM, which translates to 3 BRAMs in the device. Each BRAM is 18Kb (including parity, 16Kb without) which means that you won't have enough memory for a 16KB RAM (I'm assuming you meant bytes). To have enough RAM resources you will need to use the next larger part which has 288Kb of RAM. That translates to 32KB of RAM ignoring the parity bits.

The rest of the logic won't have any trouble fitting in the 200.

If you meant 4Kb and 16Kb then the original part will probably suffice as the LUT requirements for the 1- uart. 2- 16-bit timers and 3- external interrupts shouldn't be too much logic.

 

[shahulakthar]

Lakesh,
1. If you have design file with you then implement the design file with Device selection (xc3s50an) in xilinx ise.
2. Timer can be implemented in coding
3. there are 2 types of memory in FPGA. BRAM and Distributed RAM.
4. Frequecy can be multiplied by DCM in FPGA
5. Suggest you **broken link removed**

 

[Lokesh Waran]

Mr.ads-ee thanks for your response but there is small change in flash memory .Its 64K not a 4K .


TECHNICAL SPECIFICATIONS

64K Flash Memory
16K RAM
UART-1number
Timer 16Bit- 2numbers
External Interrupts-3Numbers
Internal Core Frequency -100 Mhz
Minimum I/O - 60 above Pins
Package type -TQFP/QFN

Xilinx JTAG Platform cable (DS-10) Compatibility

thanks for all .............

- - - Updated - - -

Mr ads-ee

The SPARTAN XCS200AN is not a TQFP OR TQG Package that is the main problem in my project .i can use only TQFP or QFP Type package .

- - - Updated - - -

Mr shahulakthar

thanks for your support and suggestions but Presently I am doing testing with the same board u suggested from Pantech solutions only,In that board in specification they are using XC3S50 TQG Package only but that is not possible to use in XC3S200 .this is the exact problem in my project

 

[ads-ee]

It still boils down to the simple question...

What is your K values in? byte or bit you never specified. That is very important as there is an 8X difference between the two.

Assuming your requests are in BYTES...
If it's in bytes then 64KB (524288-bits) will barely fit in the 1,081,344-437,312 leftover configuration flash. But the problem is your memory requirement of 16KB (131072-bits), which won't fit in the 50AN as there are only 54Kb (55296-bits) of block RAM in the device. You will have to use an external SRAM to have that much memory.

When posting on a forum you must explicitly state all information, otherwise you're wasting everyone's time trying to extract REQUIRED information from you so we can help.

 

[Lokesh Waran]

Mr ads-ee
I realized my mistakes , its thanks for ur reply and information in FPGA also i mentioned it in byte only.

 

[ads-ee]

So you'll have to punt and add a SRAM memory to your design.

 

[Lokesh Waran]

Mr ads-ee
Maximum how much external memory bytes can we add with xc3s50an ? is it possible to commuicate with i2c prorocol like EEPROM master and slave ? thank you.....

 

[ads-ee]

Mr ads-ee
Maximum how much external memory bytes can we add with xc3s50an ? is it possible to commuicate with i2c prorocol like EEPROM master and slave ? thank you.....

You can add as much memory as you need as long as you have the pins to add the memory device connections. As you only need 16KB of RAM you don't need much. You can get either serial or parallel SRAM. e.g.
serial device:
https://www.onsemi.com/PowerSolutions/product.do?id=N25S830HA
or parallel device:
https://www.onsemi.com/PowerSolutions/product.do?id=N08L63W2A
or for higher performance:
www.cypress.com/?id=82&source=productshome
or synchronous devices like:
www.cypress.com/sync_SRAMs/?source=CY-ENG-HEADER

depends on the performance and cost you need.

There's nothing stopping you from adding i2c to the FPGA and communicating with an external i2c EEPROM.

regards

 

[Lokesh Waran]

Mr ads-ee

Its really no words have with me to say thanks to you for your reply with very patience. can u send any web link for XILINX 12.3 ISE design suite step by step implementation procedure wit spartan 3AN ? Bec in CPLD only yet we are using for research so its little bit confused with FPGA to check the memory fit report like CPLD ? THANKS A LOT.............

 

[ads-ee]

Mr ads-ee

Its really no words have with me to say thanks to you for your reply with very patience. can u send any web link for XILINX 12.3 ISE design suite step by step implementation procedure wit spartan 3AN ? Bec in CPLD only yet we are using for research so its little bit confused with FPGA to check the memory fit report like CPLD ? THANKS A LOT.............

Haven't seen any 3AN step by step procedures, but then I've never had a need to look for one.

For memory fit just look at the data sheet and see how much memory is in the device. FPGA vendors tend to state the memory in number of bits so keep that in mind. Compare the number of memories and understand that the FPGA memories can usually be configured to have 1-bit, 4-bit, 8-bit, 16-bit, 32-bit width data buses. As memory requirements are usually pretty well known in advance, when you design something it's usually pretty easy to determine if you have enough up front before actually implementing the design.

regards