xilinx schematics to truth table

[dandygal]

I have a somewhat complicated Schematics design. Is there a program which could convert my design into truth tables?
If there is no such program, how can i represent the D flip-flops of the following design in a truth table?



Thanks for any tips.

 

[mrflibble]

Is this the same overdue homework/project assignment, or an entirely new assignment that just looks as if it uses the exact same schematic? If it's the same, please keep it in the same thread so people have some context.

As for this post ... you could of course make a testbench to generate all the possible input combination (as in all the possible sequences) , and then see what the output does.

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Also, just in case: http://www.asic-world.com/verilog/art_testbench_writing1.html