xilinx program can't run in quartus software successfully

[mahalakshmi r]

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process (LP1,LP2)
begin
if (LP1="00" and LP2="ZZ")
then
addout <= "00";
elsif (LP1="01" and LP2="ZZ")
then
addout <= "01";
elsif (LP1="ZZ" and LP2="10")
then
addout <= "10"; 
elsif (LP1="ZZ" and LP2="11")
then
addout <= "11";
elsif (LP1="00" and LP2="10")
then
addout <= "00";
else
addout <= "ZZ";
end if;
end process;

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above code successfully run in xilinx software and show no error in it and i got output for it... but the same program not run successfully in quartus software, it show that 'if statement' have error but i can't found any error in it if anyone know it please reply this post and its important for me......

 

[TrickyDicky]

You cannot check for "ZZ" condition on real hardware, in altera or xilinx. I dont know what xilinx did, but it probably didnt behave the way you think.

Why not post the real error.

 

[mahalakshmi r]

i have only done in simulation only.. the error made in quartus software is obtained result wrong.. 'zz' is not supported then what is the correct formet please tell me...

 

[FvM]

The term "run in quartus software" suggests that you tried to synthesize a testbench code. That's neither possible with Xilinx nor Altera tools.

 

[mahalakshmi r]

thank you for reply..
then anyone know alternative code for above one..

 

[mrflibble]

i have only done in simulation only.. the error made in quartus software is obtained result wrong.. 'zz' is not supported then what is the correct formet please tell me...

There is no correct format. What is it functionally that you are trying to do there? Don't tell me "compare to zz" because I can see that. Try some other permutation of words to explain what you are trying to do.

- - - Updated - - -

Or actually, forget that. It doesn't matter what you were trying to do with the zz's. What matters is:

1 - design your design to do whatever it should do
2 - code your design using the known to work valid language constructs

By observing 2) you will not run into this "compare to zz" problem.

The closest thing you have that you both can simulate AND synthesize is don't cares. Google "vhdl case don't care"

 

[mahalakshmi r]

what i'm trying to do is priority encoder... from LP1 and LP2, select high priority one i.e., if LP1 is 00 and LP2 is no value then it selects LP1 as output of addout...
note: here the reason for using 'zz' is that either LP1 or LP2 will have no value
this is my PG project and my project name is "ZTCAM: AN SRAM based TCAM architecture" if any one know about the details of this paper, please post information for this paper and it will be very helpful for me ...

 

[mrflibble]

Priority encoder: see my point about don't cares. It should be obvious, but apparently obvious google searches are not obvious sometimes. Google for "vhdl priority encoder don't cares". You will get a nice mix of hits, perfectly tailored to the current location on the learning curve. Happy saturday reading to you sir!

 

[FvM]

note: here the reason for using 'zz' is that either LP1 or LP2 will have no value

Digital logic nets (inputs, internal signals) can't have "no value". They are either '0' or '1'.

If you mean that values should be ignored in a particular expressions this should be easy to code,
e.g. instead of

if LP1="00" and LP2="ZZ" then

write

if LP1="00" then

 

[mahalakshmi r]

this is my part of program, remaining code presented before it calculate either LP1 or LP2 have 'zz' value it means that 'zz' value contained variable(LP1 OR LP2) not considered for further operation i.e., neither 0 or 1.
above you mentioned code formet of
if LP1="00" then
is correct bet i have to perform priority operation here
i.e., conditional operation

if (LP1="00" and LP2="ZZ")
then
addout <= "00";
please tell me alternative for 'zz'....

 

[Dan Mills]

You cannot use zz that way, use an additional signal to gate the consideration of lp1 and lp2.
So your earlier code would set lp1_en and lp2_en as approprite and you would then write:

if (LP1 ="00" and LP1_EN = "00")
then
addout <= "00";

You seem to be thinking of VHDL as a programming language rather then a hardware description language, you have to think in terms of things realisable in terms of LUTs and flipflops, Z makes sense in terms of an output signal connected to a tristatable output buffer, but that is the only place it makes sense.

For a small priority encoder, have you considered just using a lookup table in some block memory?
It might be simpler then doing it in explicit logic.

Regards, Dan.

 

[TrickyDicky]

In an FPGA, signals can only be 1 or 0, Z is not possible. Z is high impedance and only possible on output pins, and even then, you cannot check for the Z state.