xilinx pin assigment before finishing the VHDL code

[buenos]

Hi

I have a project where the VHDL-logic project has to go on in parallel to the board design.
I made the top level logic file with all the ports, and wanted to assign them to pins in the xilinx planahead. I have opened the "IO pin planning - presynthesis", but the IO port list in the planahead was empty.

Can i assign package pins when the VHDL code is incomplete? how?

 

[kvingle]

Hi



Can i assign package pins when the VHDL code is incomplete? how?

incomplete in which sense?
If your design can work with current status and give you some output then yes, of course, you can give pin constraints as well.

You can do that by
1.PACE utility
2. plan ahead
3. writing a text file (with extension 'ucf')

refer to xilinx manual for synthesis/developer guide.

 

[balavinayagam]

yes. it is possible. in the project u should have selected the correct device and its speed grade etc. . then u can preassign package pins easily

 

[buenos]

incomplete in a sense that: the internal bus statemachines, packet processing and glue logic is not finished (not even started yet), most of the generated IPs are not connected to any valid signal... they will be, but the pin assigment has to be done now, not at the end of a 2 months vhdl code development.
the planahead opens with empty io portlist.

 

[devas]

Hi,

Start a new project in PlanAhead. Do not import sources (at this time) and select your family and part.
In this empty project select File > Import IO Ports > From HDL. Select your toplevel HDL file (has only to contain the toplevel IO ports). The toplevel ports are now shown and you can drag them to the device view to assign them to pins.

Devas