buenos
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Hi
Is there a standard VHDL or verilog solution (a wrapper or something) for implementing a back-end interface for the PCI-express endpoint block in Xilinx (spartan-6) FPGAs?
The coregenerator generates 450 signals as user interface, and its not exactly a bus. It needs a bus state machine, for example OPB or Wishbone.
Is there a standard VHDL or verilog solution (a wrapper or something) for implementing a back-end interface for the PCI-express endpoint block in Xilinx (spartan-6) FPGAs?
The coregenerator generates 450 signals as user interface, and its not exactly a bus. It needs a bus state machine, for example OPB or Wishbone.