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Xilinx Modelsim simprim compilation error question

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555lin

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modelsim simprim

Compiling simprim_Vcomponents.vhd and simprim_Vpackage.vhd is without any errors but
when I compile simprim_VITAL.vhd the following error messages appear:

vcom -reportprogress 300 -work simprim C:/Xilinx71/vhdl/src/simprims/simprim_VITAL.vhd
# QuestaSim vcom 6.1c Compiler 2005.11 Nov 17 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading package vital_primitives
# -- Compiling entity x_and16
# -- Compiling architecture x_and16_v of x_and16
# -- Compiling entity x_and2
# -- Compiling architecture x_and2_v of x_and2
# -- Compiling entity x_and3
# -- Compiling architecture x_and3_v of x_and3
# -- Compiling entity x_and32
# -- Compiling architecture x_and32_v of x_and32
# -- Compiling entity x_and4
# -- Compiling architecture x_and4_v of x_and4
# -- Compiling entity x_and5
# -- Compiling architecture x_and5_v of x_and5
# -- Compiling entity x_and6
# -- Compiling architecture x_and6_v of x_and6
# -- Compiling entity x_and7
# -- Compiling architecture x_and7_v of x_and7
# -- Compiling entity x_and8
# -- Compiling architecture x_and8_v of x_and8
# -- Compiling entity x_and9
# -- Compiling architecture x_and9_v of x_and9
# -- Compiling entity x_bpad
# -- Compiling architecture x_bpad_v of x_bpad
# -- Compiling entity x_buf
# -- Compiling architecture x_buf_v of x_buf
# -- Loading package textio
# -- Loading package vpackage
# -- Compiling entity x_buf_pp
# -- Compiling architecture x_buf_pp_v of x_buf_pp
# -- Compiling entity x_bufgmux
# -- Compiling architecture x_bufgmux_v of x_bufgmux
# -- Compiling entity x_bufgmux_1
# -- Compiling architecture x_bufgmux_1_v of x_bufgmux_1
# -- Compiling entity x_ckbuf
# -- Compiling architecture x_ckbuf_v of x_ckbuf
# -- Compiling entity x_clk_div
# -- Compiling architecture x_clk_div_v of x_clk_div
# -- Compiling entity x_clkdll_maximum_period_check
# -- Compiling architecture x_clkdll_maximum_period_check_v of x_clkdll_maximum_period_check
# -- Compiling entity x_clkdll
# -- Compiling architecture x_clkdll_v of x_clkdll
# -- Compiling entity x_clkdlle_maximum_period_check
# -- Compiling architecture x_clkdlle_maximum_period_check_v of x_clkdlle_maximum_period_check
# -- Compiling entity x_clkdlle
# -- Compiling architecture x_clkdlle_v of x_clkdlle
# -- Compiling entity x_dcm_clock_divide_by_2
# -- Compiling architecture x_dcm_clock_divide_by_2_v of x_dcm_clock_divide_by_2
# -- Compiling entity x_dcm_maximum_period_check
# -- Compiling architecture x_dcm_maximum_period_check_v of x_dcm_maximum_period_check
# -- Compiling entity x_dcm_clock_lost
# -- Compiling architecture x_dcm_clock_lost_v of x_dcm_clock_lost
# -- Compiling entity x_dcm
# -- Compiling architecture x_dcm_v of x_dcm
# -- Compiling entity x_fdd
# -- Compiling architecture x_fdd_v of x_fdd
# -- Compiling entity x_fddrcpe
# -- Compiling architecture x_fddrcpe_v of x_fddrcpe
# -- Compiling entity x_fddrrse
# -- Compiling architecture x_fddrrse_v of x_fddrrse
# -- Compiling entity x_ff
# -- Compiling architecture x_ff_v of x_ff
# -- Compiling entity x_ibufds
# -- Compiling architecture x_ibufds_v of x_ibufds
# -- Compiling entity x_inv
# -- Compiling architecture x_inv_v of x_inv
# -- Compiling entity x_inv_pp
# -- Compiling architecture x_inv_pp_v of x_inv_pp
# -- Compiling entity x_ipad
# -- Compiling architecture x_ipad_v of x_ipad
# -- Compiling entity x_keeper
# -- Compiling architecture x_keeper_v of x_keeper
# -- Compiling entity x_latch
# -- Compiling architecture x_latch_v of x_latch
# -- Compiling entity x_latche
# -- Compiling architecture x_latche_v of x_latche
# -- Loading package numeric_std
# -- Compiling entity x_lut2
# -- Compiling architecture x_lut2_v of x_lut2
# -- Compiling entity x_lut3
# -- Compiling architecture x_lut3_v of x_lut3
# -- Compiling entity x_lut4
# -- Compiling architecture x_lut4_v of x_lut4
# -- Compiling entity x_lut5
# -- Compiling architecture x_lut5_v of x_lut5
# -- Compiling entity x_lut6
# -- Compiling architecture x_lut6_v of x_lut6
# -- Compiling entity x_lut7
# -- Compiling architecture x_lut7_v of x_lut7
# -- Compiling entity x_lut8
# -- Compiling architecture x_lut8_v of x_lut8
# -- Compiling entity x_mult18x18
# -- Compiling architecture x_mult18x18_v of x_mult18x18
# -- Compiling entity x_mult18x18s
# ** Error: C:/Xilinx71/vhdl/src/simprims/simprim_VITAL.vhd(10573): VITAL TISD timing generic must be a scalar form of VITAL delay

type.
# (1076.4 section 4.3.2.1.3.13)
# ** Error: C:/Xilinx71/vhdl/src/simprims/simprim_VITAL.vhd(10574): VITAL TISD timing generic must be a scalar form of VITAL delay

type.
# (1076.4 section 4.3.2.1.3.13)
# ** Error: C:/Xilinx71/vhdl/src/simprims/simprim_VITAL.vhd(10596): VHDL Compiler exiting

When I compile simprim_Vpackage_mti.vhd the following error messages appear:
vcom -reportprogress 300 -work simprim C:/Xilinx71/vhdl/src/simprims/simprim_VITAL_mti.vhd
# QuestaSim vcom 6.1c Compiler 2005.11 Nov 17 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading package vital_primitives
# -- Compiling entity x_and16
# -- Compiling architecture x_and16_v of x_and16
# -- Compiling entity x_and2
# -- Compiling architecture x_and2_v of x_and2
# -- Compiling entity x_and3
# -- Compiling architecture x_and3_v of x_and3
# -- Compiling entity x_and32
# -- Compiling architecture x_and32_v of x_and32
# -- Compiling entity x_and4
# -- Compiling architecture x_and4_v of x_and4
# -- Compiling entity x_and5
# -- Compiling architecture x_and5_v of x_and5
# -- Compiling entity x_and6
# -- Compiling architecture x_and6_v of x_and6
# -- Compiling entity x_and7
# -- Compiling architecture x_and7_v of x_and7
# -- Compiling entity x_and8
# -- Compiling architecture x_and8_v of x_and8
# -- Compiling entity x_and9
# -- Compiling architecture x_and9_v of x_and9
# -- Compiling entity x_bpad
# -- Compiling architecture x_bpad_v of x_bpad
# -- Compiling entity x_buf
# -- Compiling architecture x_buf_v of x_buf
# -- Loading package vital_timing
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Compiling entity x_buf_pp
# -- Compiling architecture x_buf_pp_v of x_buf_pp
# -- Compiling entity x_bufgmux
# -- Compiling architecture x_bufgmux_v of x_bufgmux
# -- Compiling entity x_bufgmux_1
# -- Compiling architecture x_bufgmux_1_v of x_bufgmux_1
# -- Compiling entity x_ckbuf
# -- Compiling architecture x_ckbuf_v of x_ckbuf
# -- Compiling entity x_clk_div
# -- Compiling architecture x_clk_div_v of x_clk_div
# -- Compiling entity x_clkdll_maximum_period_check
# -- Compiling architecture x_clkdll_maximum_period_check_v of x_clkdll_maximum_period_check
# -- Compiling entity x_clkdll
# -- Compiling architecture x_clkdll_v of x_clkdll
# -- Compiling entity x_clkdlle_maximum_period_check
# -- Compiling architecture x_clkdlle_maximum_period_check_v of x_clkdlle_maximum_period_check
# -- Compiling entity x_clkdlle
# -- Compiling architecture x_clkdlle_v of x_clkdlle
# -- Compiling entity x_dcm_clock_divide_by_2
# -- Compiling architecture x_dcm_clock_divide_by_2_v of x_dcm_clock_divide_by_2
# -- Compiling entity x_dcm_maximum_period_check
# -- Compiling architecture x_dcm_maximum_period_check_v of x_dcm_maximum_period_check
# -- Compiling entity x_dcm_clock_lost
# -- Compiling architecture x_dcm_clock_lost_v of x_dcm_clock_lost
# -- Compiling entity x_dcm
# -- Compiling architecture x_dcm_v of x_dcm
# -- Compiling entity x_fdd
# -- Compiling architecture x_fdd_v of x_fdd
# ** Error: C:/Xilinx71/vhdl/src/simprims/simprim_VITAL_mti.vhd(5762): No feasible entries for subprogram "vitalstatetable".
# ** Error: C:/Xilinx71/vhdl/src/simprims/simprim_VITAL_mti.vhd(5790): VHDL Compiler exiting



Please help me....what shoud I do?
 

darylz

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vhdl modelsim library simprim error

1. can you try -93 option?
2. pay attention on the compilation sequence, compile the packet first
 

YenYu

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modelsim no feasible entries for subprogram

# ** Error: C:/Xilinx71/vhdl/src/simprims/simprim_VITAL.vhd(10573): VITAL TISD timing generic must be a scalar form of VITAL delay
type.
# (1076.4 section 4.3.2.1.3.13)
# ** Error: C:/Xilinx71/vhdl/src/simprims/simprim_VITAL.vhd(10574): VITAL TISD timing generic must be a scalar form of VITAL delay
type.
# (1076.4 section 4.3.2.1.3.13)

# ** Error: C:/Xilinx71/vhdl/src/simprims/simprim_VITAL_mti.vhd(5762): No feasible entries for subprogram "vitalstatetable".


Check out this files... within those lines it is giving u syntax or linking error.

Example:
simprim_VITAL.vhd(10573) <- this file, with line 10573 is giving u error. Check out wat's wrong with it
 

glclub

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simprim error

I have get the same error when using modelsim 6.0 to complie the simprim_VITAL.vhd library of xilinx .
I have check the error line of that file, it seems that the tisd timing genetic, which is related to two entity ports of different types ( array of std_logic_vector and std_ulogic), will generate this error.
while, the tisd timing generic that relates to only one entity port of one type will not generate the error.
but ,the problem is that the simprim lib is provided by xilinx, and I think they will not make such mistake.
Moreover, I think the using of tisd timing generic is not conflict with rule of 1076.4-2000 spec, so I am very confused of this problem.how can I do?
 

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