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Xilinx MIG2.3 & pinout changes

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BenKropp

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Hi,
I need to implement a DDR2 memory controller for an existing board.
Therefore I used the core generator (10.1.03), did the settings accordingly and finished the "Create Design"
To modify the pinout I started "Update Design" and selected an ucf including the DDR2 pinout of my board.
After this, I found only the pin locations of the data ports of the board's memory interface in the new ucf (folder user_design/par). No loc assignments for addresses, controls or clocks.
Any ideas, what's wrong?
 

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