I am using Xilinx Virtex5 to build a DDR2 SODIMM memory controller. It is working well at 200MHz while having calibration problems at 300MHz. after carefully debugging and simulation, I think that Xilinx calibration algorithm didn't work well for big skews (about 900 ps between DQS and its associated DQs) at 300MHz.
Anyone has know about Xilinx DDR2 calibration algorithm, please advise. Thank you.
the delay on DQ/DQS should be configured dynamically on-the-flight to offset the variations on voltage, process, and temperature.
I did modify the ucf file generated by mig2.0 to fit into my hardware board. i believe that the modifications are correct and working well at 200mhz.
right now, i suspect that the calibration algorithm in stage1 can't deal with when DQS is right on the edge of DQ (rare case but could happen in real life).
My problem finally got solved. Right now, my DDR2 memory controller is working at 300MHz and passed some rigorous memory tests. there are two ranks in my DDR2 SODIMM and one of them is unused. The issue turns out to be that I forgot to drive the rank select signal high for the unused rank. This gonna result in the bus contention between two memory ranks. cry:
Another interesting thing is that my Virtex5 is graded speed -1. Xilinx spec said that maximum frequency is 266 mHz. I am lucky :