Xilinx ISE WebPack 9.1i sp 3, gated clock warning

[cyboman]

i'm new to digital design and don't know the tools that well. i'm using a nexys 2 fpga and Xilinx ISE WebPack 9.1i sp 3 for synthesis and implementation.

i have coded a simple johnson counter but after implementation i received the following warning:

Created netgen log file 'time_sim.nlf'.
Executing C:\Xilinx91i\bin\nt\bitgen.exe -intstyle ise -f "johnson_counter_top.ut" "johnson_counter_top.ncd" "johnson_counter_top" "johnson_counter_top.pcf"
PhysDesignRules:372 - Gated clock. Clock net clk_out is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
Implementation ver1->rev1: 0 error(s), 1 warning(s)
Implementation ended with warning(s).

the design seems to be working but i still would like to know what does the warning mean.

can someone explain what does it mean and how can i fix this warning.

any help and insights are appreciated.

 

[vipinlal]

gated clock warning

Can you post your code?

--vipin
https://vhdlguru.blogspot.com/

 

[cyboman]

Re: gated clock warning

here it is

module johnson_counter_top (
	input wire [3:3] btn,
	input wire mclk,
	input wire [4:0] sw,
	output wire [7:0] ld);
	
	wire clk_out;
	
	clkdiv #(
		.COUNTER_WIDTH(24),
		.INDEX_WIDTH(5)) u0 (
		
		.reset(btn[3:3]),
		.clk(mclk),	 
		.index(sw),
		.clk_out(clk_out)
	);
	
	johnson_counter #(.N(8)) u1 (
		.clk(clk_out),
		.reset(btn[3:3]),
		.q(ld)
	);
	
endmodule

module clkdiv #(
	parameter COUNTER_WIDTH = 24,
	parameter INDEX_WIDTH = 5)(
	
	output wire clk_out,
	input wire clk,
	input wire reset,
	input wire [INDEX_WIDTH-1:0] index);
	
	reg [COUNTER_WIDTH-1:0] counter;
	
	// binary counter
	always @(posedge clk or posedge reset) begin
		if (reset == 1) begin
			counter <= 0;
		end else begin
			counter <= counter + 1;
		end
	end

	assign clk_out = counter[index];

endmodule

module johnson_counter #(
	parameter N = 4)(
	output reg [N-1:0] q,
	input wire clk,
	input wire reset);

	always @(posedge clk or posedge reset) begin
		if (reset == 1'b1) begin
			q[N-1:0] <= {N{1'b0}};
		end else begin
			q[N-1] <= ~q[0];
			q[N-2:0] <= q[N-1:1];
		end
	end

endmodule

 

[dilinx]

Re: gated clock warning

Hi cyboman,
The warning message itself tells about problem and solution.
In FPGAs in order to avoid timing issues clock routing is given a special care...You cant let clock to go in data path. This will give a warning....
Dont gate the clock, if it is necessary, use FPGA clock resources (BUFGCTRL, BUFGCE etc)

 

[vipinlal]

Re: gated clock warning

Recently I have seen this type of code here:
http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf

Just go through the pdf.They have explained how your code is going to get synthesised under this condition and how to avoid such designs.

--vipin
http://vhdlguru.blogspot.com/

 

[dilinx]

Re: gated clock warning

Hi cyboman,
By looking at ur design it is clear that "clkdiv" module of ur design will be implemented using LUTs and FFs....that means "clk_out" is going in data path....
To avoid this use DCM or PLL for "clkdiv" module.....

 

[cyboman]

Re: gated clock warning

Hi cyboman,
By looking at ur design it is clear that "clkdiv" module of ur design will be implemented using LUTs and FFs....that means "clk_out" is going in data path....
To avoid this use DCM or PLL for "clkdiv" module.....

dilinx

i really appreciate the help, but there is a minor problem. i'm really new to digital design and fpgas in general. i'm so new to it that even when i read tutorials i don't understand them. i'd appreciate if you could help out in implementing your suggestion. how can i use DCM or PLL for clkdiv module? it would also help to know what DCM is? (i think i know what PLL is, phase locked loop).

any help is appreciated

ps. i know that it might be inappropriate to ask questions like mine on forums like these but i'm, as they say, a noob. i really would like to learn, unfortunately however i have no one near by to teach me or ask for help.

 

[dilinx]

Re: gated clock warning

PLL or DCM, u can costomize them in coregen and instantiate it in your top module (in place of "clkdiv" module).....
for more details about DCM and PLL go through xilinx FPGA user guide.....
if u have any doubts let me know.....