Xilinx ISE Timing constraints

[nag123]

hi,

My system clock frequency is 45 mhz. i am generating 90 mhz, 45 mhz and 22.5 mhz clocks using DCM and i am using these 3 clocks in my desing?

after place and route, the timing report is showing the max system frequency as 62 Mhz.

I gave the timing constraint 90 mhz . even though it is showing the max frequency as 62 mhz.

can anybody tell me what should be the max system frequency. should it be 90mhz or input 45 mhz ? what timing constraints should i use to meet the timing requirements.

 

[nxtech]

It sounds like you are bit confused about the clocking frequencies.

You said you needed a system frequency of 45MHz.

You also stated that you are using the DCMs on the device to generate three internal clock frequencies of 90,45, & 22.5 MHz each.

You listed a timing constraint of 90MHz but you did not specify what clock you set this timing constraint to.

You also indicated you have a clock frequency of 62MHz but you did not indicate what clock this is referring to.

If you are feeding your device a 45MHz clock (external) that is your system frequency.

From what you have described it sounds like you have a 45MHz system clock that you can feed to your FPGA. You have three seperate functions to implement and each one has a different clock speed requirement, thus the use of the DCMs.

Any clocks generated via a DCM are going to be internal clock signals not system signals. Also any timing contraints you apply will need to applied to the proper clock signal.

As far as what timing contraints you need to use will depend on what your timing budget is in regards to inputs and output. Specifically how long do you have to do something once data enters the FPGA to get an output based on that input. If you have multiple functions being served then you will most likely have different clocking requirements, thus different clocking domains.


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[nag123]

Can you please see the attachment ?

 

[shield]

goog material for this topic

 

[Aastik]

Hi Nag123,

after seeing your design block diagram, i suggest following points:

1. your input clock to the FPGA is 45Mhz, then you need to give PERIOD constraint to this clock only i.e. 45 mhz.

2. since your DCM is generating 90Mhz, it will automatically put constraint on 90Mhz and report the same in timing report.

3. since you are getting 62Mhz fmax for Module1 it is obvious that your module1 design is not meeting the timing of 90Mhz. since the gap is also big, you can not do anything except modifying your design/RTL in a way that it can meet 90Mhz requirement.

i hope this gives you some idea.

regards.

Added after 1 minutes:

Hi Nag123,

after seeing your design block diagram, i suggest following points:

1. your input clock to the FPGA is 45Mhz, then you need to give PERIOD constraint to this clock only i.e. 45 mhz.

2. since your DCM is generating 90Mhz, it will automatically put constraint on 90Mhz and report the same in timing report.

3. since you are getting 62Mhz fmax for Module1 it is obvious that your module1 design is not meeting the timing of 90Mhz. since the gap is also big, you can not do anything except modifying your design/RTL in a way that it can meet 90Mhz requirement.

i hope this gives you some idea.

regards.